LM5105 Failures

what you faced with is an issue related to the spike generator on switching circuit when they commutate too fast...

in particular the spikes (typ. at the SW node) above absolute maximum rating don't destroy FET and/or device suddenly because of they are very short in time, but result in a reduced lifetime and reliability of the system...

solution is (assuming your layout is also good layout) to speed down the commutations (you will pay a little in efficiency, amen): this is achieved with little gate-resistor (normally in 10R ballpark)...

it is good practice to apply this one on the HS FET (HO) but not to the LS (LO) one, since the last one increases the risk of cross-conduction (shot-through among the 2 fets)...

do you have schematic, layout and waveforms of the SW node ?

Vincenzo

Hello Vincenzo

Thanks very much for replying, your advice is certainly helpful and reassuring. I would have thought that putting a series resistor in both Hi and Lo drivers would balance the gate driver and that the programmable dead time would prevent shoot through.

I have attached a PDF file that has all the information you have requested. Not that the two traces shown, is the regulator without resistors and the other is with resistors fitted to both the HI and LO driver. My apologies the schematic did not copy accros all that well, the FETS are a little mangled..!

I hope this helps and I look forward to your reply.

Cheers

Ant

schematic is ok, just little corrections:

- apply a divider to EN pin so that device turns on only when VIN is at a certain level (i.e. 8V for a 5V output) to avoid input current inrush and/or failures at start-up

- C58=100nF is more than enough (change it if cheaper than the 220nF one, otherwise nevermind)

- use 10R gate resistor on HS only

- remove the 10R gate resistor from LS, mandatory!

while layout needs a massive improvement, not only for the LM part, since it looks like you routed power nets as signal ones...

please have a look at the attachment or refer to any of our EVM's layout...

Vincenzo

1346.Layout Guidelines for Switching Power Supplies.pdf

Hello again Vincenzo

Thanks very much for your reply, I shall make the changes you have recommended and will give it another go. I will also re hash the routing to improve the power plane. 

Thanks again

Cheers

Ant

Hi Vincenzo,

Thanks a lot for your information.

I happened to cross this topic, but I don't understand why you say" but not to the LS (LO) one, since the last one increases the risk of cross-conduction (shot-through among the 2 fets)...".

first , the dead time control can prevent cross-conduction;  

second, if lower mosfet conducts ( ON)faster than the top one, will this increase cross conduction too?then we have to increase the dead time.

third, if lower mosfet shuts off too fast, will that increase overshoot on the bottom mosfet too?

thank you very much,

Interesting that this is still being looked at..! 

I have had almost given up on the chip and was seriously thinking of looking for something else when I decided to see if the enable line had anything to do with the failures.  One of my previous designs had this line latched high permanently high and I noted that the failure rate with the few boards I had was zero. For those boards, turning off the supply was just a matter of setting the PWM signal to the LM5105 to 0%. The reason I had wired in the enable line to the processor was to turn off the LM5105 to minimise power consumption when it was not required, it was there as a feature, why not use it..!

I have modified as many of the latest boards that I have been able to lay my hands on by cutting the LM5105 enable line and tying it high to the 12V supply line. I have had no failures since. Prior to this modification, I had altered the firmware to see if altering the relationship between the PWM and the enable line would fix this problem.  (lowering or raising the enable line with the PWM signal on or off, this did not alter the reliability)

For me, the fix has been to just latch the enable line high and manage the on off cycle with the PWM signal.

Ps. I see sense in your argument, there should be no reason to fit series resistors to the FETS

Cheers

Ant

@ John

this is different story from cross conduction caused by the drivers; I'm talking about the dV/dt immunity.

in brief, when HS turns on the parasitic capacitors of the LS fet form an impedance divider that, when not well balanced, could cause the voltage on the Gate to raise up to the Vgth... it is a very short event, but adding a gate resistor to the LS increases this risk...

refer the attachment for details

Vincenzo

3513.DV-DT Immunity Improved in Synchronous Buck Converters.pdf

Hi Vincenco,

Thanks a lot, very helpful, I forgot this.

Thanks a lot, Ant,it is very useful experience.

I also have experience using the LM5105 in a solar battery charging circuit. For anyone else who happens upon this thread, here are some suggestions based on the circuit in the solarpower.docx schematic. Run the LM5105 Enable pin from the microcontroller so you can control it. Don’t just tie it high. When EN is low the HS and LS FETs are off. However when EN is high, the output follows the PWM input (more or less). If the PWM is held low (at startup for example), the LS FET will be on. If the LS FET is latched on like this you have basically a dead short from the +12V battery through F2 through L4 through Q13 to ground. It would probably make sense to slap a pull down resistor on EN as well to be safe during startup. Holding the PWM signal high is probably a preferred resting or startup state as the circuit can probably survive for a long time even if Q8 were left on. Q3 latched low is a scary scenario where the battery is basically shorted to ground. L4 the 10uH inductor will only limit current di/dt for pulse lengths in the neighborhood of the designed switching frequency. For slower pulses the inductor will quickly saturate and the pulses start to look like DC, shorting your battery to ground. I would start to worry about Q3 if it were latched low for as little as say 20us.

Also, the inductor seems maybe a little small for 100kHz. I think the current ripple is going to be quite large, maybe 3 or 4A peak-to-peak which is approaching 100% of your full scale 4.5A target.

I would be inclined to move Q1, the reverse blocking FET, after L4 on the battery side of the circuit. In this position, when turned off, it would prevent accidental discharge of the battery through LS FET if is momentarily latched at startup. Also, when off, the circuit can operate normally at low currents through the body diode of the FET. This prevents the inductor current from going negative at low currents. Though to prevent all reverse conduction it would have to operate very fast.

If I were making a charging circuit in the 4A range, I probably wound't mess with a synchronous converter. Non-synchronous converter has a lot fewer failure modes.

I am also not comfortable with the disconnect/reverse protection switch Q2 in the negative line. But that is probably a different discussion.