Hello,
I'm working on a board that has a Spartan 6 FPGA interfacing with a single DDR3 8-bit chip (shown below).
When the board powers up the FPGA configures the DDR3 successfully. If I attempt to reset the FPGA memory controller core the TPS51116 outputs all go to zero. If I were to pull S2 and S3 low and then high the chip is enabled again. I've scope'd this and observed that all the outputs of the TPS51116 go higher and higher until they reach that 115% threshold. So this is the reason why the chip is resetting, I don't understand why the voltage is rising and rising, why the chip seems to have a difficult time in reducing the voltage on the output.
I've attached two scope traces.
This first one shows a slow capture of when the board is powered on (before the FPGA is programmed and the memory controller starts configuring the DDR3), then after it has configured the DDR3 and the large drop is when I reset the memory controller core (Not the FPGA).
This second image is a zoomed in view of the behavior when the soft reset button is pressed.
As you can see the voltage rises and rises until it reaches nearly 1.8V which is the 115% of 1.5 = 1.725V
The schematic of the page is attached3678.temp.PDF
Some information about the design.
-Powering a DDR3 chip @ 1.5V VDDQ, .75 VTT, .75 VREF
-D-Cap Mode ( I know the schematic shows that there are ceramic capacitors on the output but I have since changed them to two 150uF OSCON caps with 40 mOhms each of ESR
-The current trip resistor on this schematic is 4.32K but I have since changed that to 4.99K
-The 5V regulator is mislabeled as saying 1.2V
Any help as to why this chip is doing this would be extremely appreciated.
A sincere thank you to anyone who can help in advanced.
Dave
