Hello,
Please see the attached file as UCC28070 Phase Management Demonstration.
In attachedfile page 2, there is discription as below.
"When the phase is restarted, there is a short time-delay as the CAO voltage decreases from saturation back down to its normal level, during which time the input current for that phase may increase to the peak current limit."
Could you please kindly let me know the circuit for avoid this input current increasing?
Best Regards,
Ryuji Asaka
Ryuji Asaka