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TPS56121 soft start slew rate trouble

K. Sasaki14
Guru 10200 points
Other Parts Discussed in Thread: TPS56121

TPS56121 soft start slew rate trouble is observed.

Please refer to attached file about detail.

I'm thinking that the cause is due to voltage drop of EN/SS pin during calibration operation.

I'd like to know  what happens in the device when EN/SS pin voltage drops during calibration.

Is there possibility of slew rate trouble?

Please let me know if there are other conceivable phenomenon.

3821.TPS56121 soft start slew rate trouble.pdf

  • 0
    TI__Expert 4350 points

    Kohei-san,

    Thank you for your interest in TI parts. I looked at the waveforms in your attachment and discussed them with design. It is not recommended to pull down on EN/SS during calibration. There are several circuits that can misbehave when EN/SS is pulled low during calibration.

    One of the results is that when the external pull down pulls EN below 0.4V, the device will be ready to start switching and will provide gate drives once the SS voltage exceeds about 0.7V, even though calibration was not finished. When calibration is corrupted in this manner, then the soft start current will not be the accurate 10uA as desired, but it will be a less accurate 40uA. This is why the SS time is much faster, as you have observed.

    An even bigger issue is that the calibration itself will be corrupted, which can result in the wrong Fsw, an incorrect OCP, and possibly a disabled OCP.

    You may be able to design around this by adding a logic gate to the PLD output that is configured to only be active after the TPS56121 soft start is finished.

    Regards,

    MC.

  • 0 in reply to Martin Cardella
    Guru 10200 points

    Martin-san,

    Thank you for your answer. I can answer to customer.

     

    I have another question. Please let me know about the following.

    When EN/SS pin  is connected to capacitor only, EN/SS pin voltage rises up to about 5V.

    In the case of EN/SS pin is connected to PLD, EN/SS pin voltage can't rise up to about 5V when PLD leak current is 10uA.

    Now according to my customer's observation, EN/SS pin voltage rises up only to 2.5V.

    Is it possible to operate normally if EN/SS pin voltage rise up to over 1.4V?

     

    Best REgards,

    Kohei Sasaki

  • 0 in reply to K. Sasaki14
    TI__Expert 4350 points

    Kohei-san,

    The EN/SS is pulled up to BP with the internal 10uA current source, so if there is only a cap connected to EN/SS it will rise to about 5.5V.

    However, there is internal logic that changes state when the SS_int reaches 0.8V. There is approximately a 0.7V level shift from SS_int to SS/EN pin, so when SS_int reaches 0.8V, EN/SS pin reaches approximately 1.5V. If the PLD clamps the EN/SS pin to 1.4V, the device will potentially never declare "SS_done". The tolerance on the 0.7V level shift is such that you need to allow the EN/SS pin to exceed about 2V in order for the device to enter steady state operation. 1.4V is not high enough.

    On a related note, if the intention is that the PLD is used to disable the device during power-down, the design must ensure that the PLD is capable of discharging the SS cap quickly. Specifically, as the PLD discharges the SS cap from 0.8V to 0.3V, it must discharge the SS cap in that voltage range in 2uSec or less. This is because within that range, the device will actively discharge the output bus by keeping the LFET ON. Above 0.8V there is no change to operation. Below 0.3V the device is disabled. In the range from 0.8V to 0.3V, the device will actively discharge the output bus.

    Depending on the output bus capacitance and the amount of stored energy, there can be enough energy to damage the LFET. So, the discharge time from 5V (or 2V) to 0.8V doesn't matter. The discharge time from 0.3V to 0V doesn't matter. But the discharge time from 0.8V to 0.3V should be 2uSec or less.

    Regards,

    MC.