TPS40400 and SW rise time

Jay,

The data you mention is to be expected. The CSD FETs switch extremely rapidly.

If you look at the internal architecture of the TPS40400 or any similar controller, you can see that the BOOT cap is charged by BP6 via the internal BOOT diode. So even when you add a series BOOT resistor, the current for the turn ON of the high-side FET (HFET) will simply be drawn directly from BP6 through the BOOT diode. The impedance of the diode during a gate pulse is non-linear, but will be somewhere in the range of a few (≈5) ohms. So your external BOOT R ends up being in parallel with this diode impedance, which is why you should see a slight difference as you vary the BOOT R from 0-ohms to about 10-ohms, and then very little difference higher than that.

This is true right up to the point at which the SW node starts to lift from ground, at which point the BOOT diode becomes reverse-biased. But by definition, the HFET is already ON enough to move the SW node, so the series BOOT R has only a very limited effect on the SW node slew rate.

If you need to slow down the slew rate further, you will need to consider a series gate resistor. This will have a direct effect on the slew rate, and you will be able to have more direct control on it. However, the 40400 uses the gate signals as a reference for the next switching edge, and to avoid shoot-through, so if you add a series gate resistor, you must also add an anti-parallel diode with this gate resistor. Connect this diode anode to gate, cathode to 40400. The purpose of the diode is to maintain the rapid turn-OFF of the HFET.

The BOOT cap needs to be refreshed by the BOOT diode every time SW is low, but with a resistor higher than about 10-ohms, the BOOT voltage will start to sag. You should not go any higher than 10 or 15 ohms for the BOOT R.

The slew rate at the SW node will be somewhat dependent on the load. The 40400 incorporates dead time between the FETs in order to avoid shoot through. So there will be in the range of 25nSec of time between turning OFF the HFET and turning ON the LFET (and vice versa). During that dead time, it is the inductor current that commutates the SW node low (or high). When load, and therefore inductor current is low, the current available to charge or discharge the parasitic capacitance at the SW node is also low, so the slew rate will be lower. At no load, or any load that is less than half the p-p inductor ripple current, the inductor current will be negative (direction from load to FETs) at the time when the LFET turns OFF. This current will commutate the SW node from low to high, but no where near as rapidly as is with an active turn ON of the HFET.

Regards,

MC.

Is there another footprint compatible fet that might slow rise time down a bit? We don't have pads in design to add gate resistance. We have 2 22uf ceramic caps on input and we are doing 12v to 1v. is that sufficient? I am seeing 300-400mv of noise injected on 12v input plane. is that expected? About 80-100mv seems like low freq noise (using 20 MHz cutoff) and the rest is high freq noise. Measuring with coax attached to input cap. 

Thanks,

Jay

Jay,

TI only has NexFETs which all switch extremely rapidly. You may be able to find slower FETs from another vendor that have the same footprint and pinout, but I can't help you with that search.

The noise being injected back to the 12V is inevitable. The speed of these FETs is such that the closest caps, which should be 1210 or 0805 MLCCs, should be butted right up against the appropriate pins of the FETs, as close as your manufacturing rules allow. That way the extreme di/dt will result in less delta-V on the 12V bus.

At this point it would be best if you could post the waveforms you are getting so that I have a better idea. You want to measure right across the FETs from VIN to GND.

Regards,

MC.

Which plots in particular? Input noise plot? Do you want a bw limit put on scope trace?

Thanks!

Jay

Also, could a small cap from HDRV to GND also slow rise time on SW node?  Ideas for values?

Thanks,

Jay