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LM2593 Phase margin correction.

martin b
Intellectual 560 points

Hi.

I have plugged in the following values in WEBENCH for the LM2593.

Vin(min)=9V

Vin(max)=20V

Vout=5.0V

Iout=1.0A

When opening the design I received a warning the phase margin was too low (~12.xx deg). I change the value of the output capacitor for one with a higher ESR and the phase margin improved to 56.7deg. Looking through the LM2593 data sheet for Figure 1 (Adjustable Output Voltage Versions) there is the inclusion of Cff(feed forward capacitor) which is used the when the output voltage is greater than 10V or when COUT has a very low ESR. I’m using the fixed 5.0V version and my question is have I correctly improved the phase margin, or is there a better/other way of doing this, and yes I’m a power supply novice trying to get a working design.

 

Thanks for your help.

Martin. 

  • 0
    TI__Guru 67495 points

    The best plan is to always use Webench, since that software takes into account many details of the design.  The phase margin can be improved either by using a cap with a higher ESR or a CFF.  A cap with a higher ESR will give slightly more output ripple and the ESR will change with temperature, however it will work.  Using CFF means that you will have to experiment with the value to find the optimum stability.  It would be prudent to and a place on the PCB for a CFF if you wish to experiment.  Also, the PCB layout is a big part of the design.  We will be happy to look at your layout when you are ready. 

  • 0 in reply to Frank De Stasi
    Intellectual 560 points

    Hi Frank. Thanks for your very valuable input and assistance. Figure 1 of the data sheet shows CFF across R2 as the regulator is the adjustable type.  

    (1) I'm assuming CFF can still be employed between the output and FB pin of the fixed output regulator?

    (2) Is it possible to edit the cct in WEBENCH, add CFF and simulate different values? ,,, as the phase margin was initially too low, the output ripple was very good,

    (3)  so,,, is there a base value of CFF to add to a prototype and have a reasonable expectation the out put will be stable? or is this layout specific?

    I've included a pic of my intended proto board, which will closely resemble the final if all goes well. I haven't yet added CFF. The footprints for Cinx=10uF, and chf=0.1uF are not initially going to be populated.

    Thanks again.

    Martin.

  • 0 in reply to martin b
    TI__Guru 67495 points

    For the fixed device you would not use a CFF; only if you wanted to use the ADJ with FB resistors.  I think you will be OK with the fixed device and the capacitor that gave the good phase margin on Webench.  I do not think that Webench allows you to add a CFF for this part.  For the layout I would try to move Cout on the other side of the inductor so you can ground it near the diode ground.  Also, the ground pin of the device should be connected to the DAP.  This would mean moving your connections to the flag and FB; maybe on a second layer.  I think you will need chf, so leave it there.

     

  • 0 in reply to Frank De Stasi
    Intellectual 560 points
    Thanks for your help Frank. I'll implement your recommendations.

    Cheers
    Martin