TPS2363 Power up sequence

Hi all,

I have not gotten your answer about this post.
Could anyone give me answer?

Best Regards,
Kohei Sasaki

Hi all,

I got update information. I will attach current observation information.

TPS2363 Power Supply v2.pdf

Best Regards,
Kohei Sasaki

Hi Kohei,

I have contacted the appropriate engineer to help address your questions.

Thanks!
Alex

Hello Kohei,
I will look into this . It may be a bit of involvment to decipher all.Brian

Brian-san,

Thank you for your response.

[Timing of adding 3.3V#0 and #1]
Thsese 3.3V is another power rail. So there is possibility that each power-on timing deviate a little.
FAULT is not detected if the wait time between 3.3V#0 and 3.3V#1 is more than dozen ms.
Thus I'm concerned about any abnormal operation occurs when power-on timing between VAUXINA and VAUXB deviate a little.


And our customer requires due date for answer. They would like to get answer as soon as possible because there is possibility that they must change design. So could you let me know the due date target about the following questions?
- Why does the FAULT detection phenomenon occur?
- Does TPS2363 have required power-up sequence? If it is yes, please let me know the reason.
Our customer make 3.3V from 12V, so it is difficult to add 3.3V at first.
- Why did RSVD bit change?


Best Regards,
Kohei Sasaki

Kohei-san,
I will have a reply by next Wednesday. Unfortunately, I am out of office today and Monday. I have ordered some hardware and will have it Tuesday and will try to resolve as early as I can.
Brian

Brian-san,

Thank you for your support. I'm looking forward to getting your reply.

Best Regards,

Kohei Sasaki

Brian-san,

Sorry for pushing you. Could you share current progress? Our customer requires the current report.
And also, I would like to share our customer's waveform. So could you tell me your e-mail address.
According to past test, FAULT signal is not asserted when AUXINA is added before AUXINB. FAULT signal is asserted when AUXINB is added first.

Best Regards,
Kohei Sasaki

Sasaki-san

A detailed schematic and any further waveforms would be helpful.  We don't post internal emails on public pages.  You can get my contact info from our local sales team.

• 3.3v Aux is used for internal bias.  It comes from one of the Aux. 
• The DS pg 11 requires 3.3v to come up prior to +12v.  Both 3.3v inputs need to come from the same source (+3.3v Aux can be tied to +3.3v).  +3.3v Aux needs to be up 1st (or with main +3.3v) presumably so that uv and POR circuits are alive prior to +12v.  Both +12v inputs need to be from the same source also. 
• STATA (04h) and STATB (05h) indicate Fault A/B bit in 'Fault' in all conditions you sent.  These are simply mirrors of the actual Fault A/B pins and don't indicate a normal power up for either condition.  VauxFA/B BIT is also set so an ocp event occurred on the AUX A/B outputs.  These are set for 400mA (assumed since there is no pull up shown for AUXHIA/B pins and these have internal 40k pull downs.  If you pull them high, 800mA can be set in case an ocp event initially triggered this event.  Try sequencing 3.3v AUX prior to +12v 1st.  STATA also indicates a +3.3v OC event.
• In looking at the data base, the RSVD (Reserved) should be low all the time.  I can look deeper, but I don't believe this is a root issue with what we know now.
• Can you more clearly label which status scenario goes with which test condition?
• Again, a schematic showing pull up and down resistors/values can help.

Brian

Brian-san,

Thank you for your support.
Could you send e-mail to "sasaki-k@clv.macnica.co.jp"? This is my address.

Best Regards,
Kohei Sasaki

Brian-san,

You said both 3.3v inputs need to come from the same source. Does this mean 3.3V for system (not for AUXIN A/B) must be same source?
Where is this written on datasheet? Our customer's 3.3V for system is 3.3V#0 and 3.3V#1, these are not same source.
If this is so, the reason is needed for the following,
- Why does 3.3V for system have to be same source?
- Why do AUXIN A/B come up first? What does it occer if we can't meet this requirement?

"Try sequencing 3.3v AUX prior to +12v 1st.  STATA also indicates a +3.3v OC event."
Is this thing which you observed? Does STAT indicated 3.3V OC event although 3.3V AUX is added first?

Best Regards,
Kohei Sasaki (sasaki-k@clv.macnica.co.jp)

The main 3.3v and 12v supplies need to be from the same source.  3.3v AUX can be tied or not tied to the main 3.3v lines.   3.3v Aux needs to preceed +12v per the DS since the AUX supply is used for bias in the IC.  Will work via email from here out.

 

Brian