This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ76PL455A-Q1 External Power Supply and Grounding

Other Parts Discussed in Thread: BQ76PL455A-Q1

Hi,

I am student at Istanbul University. And we want to monitor and balance battery packs in our project.

I have 80 series lithium polymer battery pack. That means 336 Volts . My first problem is about grounding. "16-Cell EV/HEV Integrated Battery Monitor and Protector with Passive Balancing Reference Design"  in this design AGND1 , AGND2, AGND3 ,DGND1, DGND2 and DGND3 tied together. I think these ground pins must be seperated. Because AGND1 and AGND2 must be tied to lowest battery cathode in row and other ground pins should tie to external power supply ground. I am confused between reference design and datasheet. 

Other problem is datasheet doesn't give enough information about external power supply?
Should I connect TOP pin when i use external power supply?
Can i supply  VDIG and VIO pins with 3.3 Volts?
Should i NPNB pin float?

Thanks.

  • Based on our testing for BCI, ESD and EMC, the best results are achieved with a common GND plane. 

    If supplying the device externally, we recommend applying 12V (min) to the NPN collector circuit. VP must be under the control of the bq76PL455A-Q1 to ensure it is properly handled in shutdown. VDIG connects to VP. VIO attaches to the VDDIO of the host controller, and is also used to supply any pullups on the TX/RX/FAULT_N pins. Please see the attached reference schematic for using the bq76PL455A-Q1 as a communications bridge for an example of this implementation.

    bq76PL455A-Q1 Bridge Reference Schematic.PDF

  • Thanks for your reply.

    I understand that, I had yo use NPN based circuitry.  I will use digital isolator (between BQ76PL455A-Q1 and microcontroller) , temperature transducers  and inverter (for wake up pin). For these components i need 3,3 V or 5 V regulated supply connected to the BJT emitter (as VP , VDIG). And if i supply digital isolator 3,3V, i will connect 3,3V to VIO pin. So , BJT Emmitter Voltage could be less than 5,3 Volt in running mode or sleep mode?

    First stack communicate with microcontroller and microcontroller manage the BQ76PL455A-Q1. But  upper stacks communicate with first stack BQ76PL455A-Q1. So what should i do to the WAKEUP pin for upperstacks?

  • You really need to provide an isolated 12V supply to the NPN collector, and have the bq76PL455A-Q1 control VP/VDIG. An LDO on the 12V supply would also source the VIO and digital isolator VDD and WAKEUP signal (after an RC delay to allow time for 12V to come up).  

  • I also want to supply BQ76PL455A-Q1 from external source in our new monitoring board design. Main goal is to minimize current consumption from the cells. I understand that there no possibility of disconnecting TOP pin from the top of the stack. Is there any information about current consumption through the TOP pin when collector of NPN transistor is powered from external source?
  • Unofficially, it is possible to supply VP with an external source, though there a few things to consider:

    1. The VP supply must be turned off when the device is in shutdown. The device was designed to always control VP, and supplying VP while the device is put into shutdown mode may lead to higher than expected current consumption/leakage while in shutdown.

    2. The internal regulator must be turned off by setting DEVCONFIG[REG_DISABLE], else there will constantly be a VP_CLAMP fault set.

    3. VP should be supplied with ~5.3V to get the highest possible overhead on the communications signals (V5VAO supplies the COMM domain, but V5VAO is supplied from VP after the device starts up), therefore the best possible communications robustness in the presence of noise. 

    Use of the device in this way is up to you... It has not been characterized by TI.