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TPS2490 Calculator Tool and Reference Design Values

Keith Wilbern
Prodigy 60 points
Other Parts Discussed in Thread: TPS2490, TPS24770

Hello and I apologize if this question has been address previously.

I am in the process of creating a proto based off the TPS2490 Hot Swap reference design for a 12V, 60A application.  I found the calculator tool for this part and was going through the process of verifying all the schematic values that were used in the reference schematic.  The first issue with the calculator tool is that there isn't an option to choose multiple FETs.  I have tried to enter the same values from the reference design and can't seem to get the calculator tool to come up with the same values for the power limiting.  There are cells in the spreadsheet dealing with power limit and Vprog that are always Red.  It might be that the tool doesn't know about parallel FETs.  I tried to go back and half the input current but that didn't seem to help.  Is there some cell that needs to be modified to account for multiple FETs?

Thanks,

Keith

  • 0
    TI__Genius 12621 points
    Hi Keith,

    We have this detailed application note which discusses hot swap design calculations, including “Considerations for Parallel MOSFETs”:

    www.ti.com/hotswap --> “Technical Documents”  “Robust Hot Swap Design”.


    For this design, if only 12V is needed then TPS24770 would be a much higher performance device and can work with smaller sense resistor voltage (10mV for TPS24770 vs 50mV for TPS2490) which means less wasted power dissipation.

    TPS24770 = 10mV * 60A = 0.6W of power dissipation through the sense resistor. TPS2490 = 50mV * 60A = 3W of power dissipation.

    This means around 2.5W of power savings, which would could save on lifetime cost of ownership.

    We also have newer design tools and tutorial videos to make designing with the TPS24770 much simpler.

    Check out the design tool at www.ti.com/hotswap --> “Tools & Software”  “Design Calculator Tool”

    And our video tutorials on how to use the tool at www.ti.com/hotswap --> “Support & Training”

    Thanks,
    Alex
  • 0 in reply to Alex Triano
    Prodigy 60 points
    Alex, thanks for the quick response. Is there some way to arrive at the same values as the TPS2490 reference design? I have probably gone too far down the path with the TPS2490 to scrap it and start over.

    Thanks,
    Keith
  • 0 in reply to Keith Wilbern
    TI__Genius 12621 points
    Hi Keith,

    I understand. I will attach the calculator spreadsheet tomorrow filled out with the PMP9616 design requirements/calculations.

    By the way, welcome to the E2E forum!

    -Alex
  • 0 in reply to Alex Triano
    TI__Genius 12621 points

    Hi Keith,

    The spreadsheet is attached.

    TPS2490Tool_revG_PMP9616.xls

    However the issue is that cell C83 is not accurate. Cell 83 should be read from the SOA curve of the CSD17570 datasheet as described in the sample figure to the right in the spreadsheet.

    So you should check the MOSFET datasheet, look at the Vds curve at the point of cell C82 (4.232V) and then look at how much current the IC can handle for a pulse duration equal to the fault time (cell C75). However, the effective fault time may be higher than cell C75. Take a look at the actual waveform from the PMP9616 test results:

    From this waveform we see that the input current is ramping up due to the slow slew rate of Vgate/Vout. So if we estimate all the energy from the I-IN curve as an effective pulse of energy with a peak of 27A for a duration of t-effective, then t-effective would be around 2ms. So instead of checking the SOA curve for a pulse of 0.5ms (the original fault time), instead we should check the curve for a duration of 2ms.

    Also, at the time PMP9616 was created, the SOA curve of the CSD17570 was much higher (it was around 200A for a 0.5ms pulse at 4.2V Vds - which was used in the original calculations). The datasheet was updated after more accurate testing was conducted to measure the true failure point of the MOSFET.

    So if we review the design again to consider all worst-case conditions, we should change that one cell from the spreadsheet, cell C83 from 200A to instead look at the new CSD17570 SOA curve at 4.2V Vds for 2ms which would be about 50A. If we enter that value, we see the design may no longer be safe for a start-into-short circuit test at elevated temperatures.

    Instead, a stronger SOA MOSFET should be used such as CSD17556. It has much stronger transient power performance.

    As shown in the TI Design waveforms, the design does work to protect start-into-short at room temperature and using typical values. But it depends on the level of design margin required for the application such as whether to consider protection against fault conditions at elevated ambient temperatures.

    Thanks,

    Alex