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TPS40101 Vssos meams

Other Parts Discussed in Thread: TPS40101

Hi

I have a simple question about Vssos on the datasheet.

The Vssos means 350mV in the following block?

If it so, the start point of Vout soft-start varies between Vss=300mV~800mV.
Is that correct?

Regards,

Koji Hamamoto

  • Hi Koji,

    350mV is the SS offset votlge. It means the part starts to swtiche when SS pin voltage is reaches 350mV.

    Thanks

    Qian

  • Hi

    Thank you for your support.

    The SS offset voltage that you mentioned above is the following spec?

    The part starts to swiche was 660mV on our mesurement. I would like to confirm the starting voltage is OK or Not.

    Regards,

    Koji Hamamoto

  • Looks like the VSSOS in the spec table refers to the SS offset voltage. I have no idea why the typical value of VSSOS is not 350mV.

    Regarding your test, do you mean the part starts to switch when SS voltage reaches 660mV? The possible reason is there is some initial lag from the SS pin voltage to the voltage applied to the error amplifier. This information is presented on datasheet page 23.

    Thanks

    Qian

  • Hi Qian,

    Thank you for your quick reply.

    >Looks like the VSSOS in the spec table refers to the SS offset voltage. I have no idea why the typical value of VSSOS is not 350mV.

     That is why I got confused.

    >Regarding your test, do you mean the part starts to switch when SS voltage reaches 660mV?

      Yes. Please see the following waveform.

    >The possible reason is there is some initial lag from the SS pin voltage to the voltage applied to the error amplifier. This information is presented on datasheet page 23.

       I found the explanation for this lag. That must be Tss on the datasheet.

       I think Tss means Vss=350mV (=Vssos). And Tss has some variation so that Vssos is 300mV(min) ~ 800mV(max).

       

    Regards,

    Koji Hamamoto 

       

  • Hi

    We still have the issue which is mentioned above.

    And I have some additional questions.

    >The possible reason is there is some initial lag from the SS pin voltage to the voltage applied to the error amplifier. This information is presented on datasheet page 23.

       Does the lag mean the following "Tss delay"=Vssos?

        

    Also does that delay depend on Css?    I do not think that delay does not depend on Css.

    However on the customer evaluation the delay seems to be dependent on Css. 

    Our concerns is that delay may exceed the specification on the datasheet. Because the specification(Vssos) on the datasheet does not specify the Css condition. 

    Please let me know if you have any question.

    Regards,

    Koji Hamamoto

  • Hi

    We still have the issue which is mentioned above.

    And I have some additional questions.

    >The possible reason is there is some initial lag from the SS pin voltage to the voltage applied to the error amplifier. This information is presented on datasheet page 23.

       Does the lag mean the following "Tss delay"=Vssos?

        

    Also does that delay depend on Css?    I do not think that delay does not depend on Css.

    However on the customer evaluation the delay seems to be dependent on Css. 

    Our concerns is that delay may exceed the specification on the datasheet. Because the specification(Vssos) on the datasheet does not specify the Css condition. 

    Please let me know if you have any question.

    Regards,

    Koji Hamamoto

  • HI Koji,

    Where is the delay specification on the datasheet?
    Can you provide the screen shot?

    Thanks
    Qian
  • Hi Qian,

    No, actually the delay does not specify on the datasheet. 

    The Vssos is specified as 200~800mV on the datasheet.  However there is no Css conditions.

    Does the Vssos depend on Css?

    On the customer evaluation, the Vout starts to switch when the Vss is 660mV.  Also it seem to be dependent on Css.

    (I do not know why the typical value of Vssos is not 350mV.)

    We would like to know how much is the start point of switching. 

    >Regarding your test, do you mean the part starts to switch when SS voltage reaches 660mV?

    >The possible reason is there is some initial lag from the SS pin voltage to the voltage applied to the error amplifier. This information is presented on datasheet page 23.

    As you mentioned above, there is some initial lag in addition to Vssos.  So that, we have to consider to add some lag to Vssos.

    (For example; 

        If Vssos is 350mV and the lag is 100ns, the switching does not start even though when the Vss reach 350mV. It start when Vss reach at more than 350mV.    

        (The voltage of Vss depends on Css)

    Is my considering correct?

    Regards,

    Koji Hamamoto

  • Hi Koji,

    When SS pin voltage is lower than offset voltage, the COMP stay at 0V. When SS pin voltage is larger than offset voltage, the COMP starts to rise up from 0V. It will take some time for COMP voltage rise from 0V to PWM ramp valley. Before COMP rises above ramp valley, there is no switching and Vout will not rise.

    The PWM ramp valley is listed in below spec table.

    I think what customer might be interested is the total time from "SS start to rise" to "Vout is regulated" and its variation.

    Customer can consider to use below equation to calculate the total time.

    Ttotal=Css*(Voffset-max + VFB)/20uA

    Here "Voffset-max" is the maximum offset voltage which is 0.8V.

    VFB is 0.69V.

    Considering the variation of Css and hand over time from SS voltage to internal reference voltage, use 2*Ttotal to get some margin.

    If there is a power sequence between TPS40101 circuit and other power rail, customer can also consider to use the TPS40101 PGOOD pin for power sequence.

    Thanks

    Qian