WEBENCH® Tools/LM5116: LM5116　Return is not stable.

Can you tell me what your switching frequency is? LM5116 has a minimum off time.

Hi john,

Thank you for your reply.

Switching frequency is 100kHz.

best regards.

The minimum off time may be as high as 580 nsec, so that may be your problem. I have alerted the support group to look at your issue.

I think John is on the right track. At 100kHz the full clock period is 10us. The built-in required off time of 450ns (580 max) means that the control loop hits its limit at 94.2% duty factor. But the rough calculation says it should work, and so does Webench.

Let's look at a different angle. The LM5116 uses emulated peak current mode control. This approach is best when applied to applications where the input voltage is substantially higher than the output voltage which results in short On-times of the high side switch. In those applications it is easier to get a clean current sample during the Off-time which is comparatively long. However, in your application you are attempting to run in a situation approaching drop out: Very long On-time and very short Off-time. So for the LM5116 to properly emulate the inductor ramp, the layout between the IC and bottom MOSFET must be ideal. This particularly concerns the CS, CSG and Gnd lines of the IC. Additionally the routing of the RC-snubber on the switch node can create sensing issues. If you look at equation 2 on page 16 of the data sheet: IR = 5 μA/V x (VIN - VOUT) + 25 μA you can see that as Vin gets lower, the ramp signal approaches zero which will cause stability issues in the loop.

I guess my next question is whether your PCB layout was based on the original evaluation PCB design example? It may be a good exercise to take a stock EVM and see if it will work properly in comparison.

Looking briefly at the document AN-1713 for the LM5116-12 (a 12V output 5A EVM), the designer chose to rate the minimum Vin at 15V (3V of drop-out margin - Compare this to your application where it is 0.9V) Also reviewing AN-1596 for the 5V LM5116 Evaluation Board they give 2V overhead.

So I think you should compare the layout of the current sense path against the factory boards and see if you can improve the signal integrity of the current sense path of the bottom side MOSFET.

Hi,Martin.

Thank you for your reply.

PCB layout is original.The CS and CSG pins are not Kelvin connected.However, CSG is strongly connected to PGND.

(※I attached PCBlayout)

It is possible to lower the switching frequency from 100 KHz to 65 kHz. Is it effective for improving stability?

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About the event is attached.

1. Vin=20V～30V Vout=17.1V 0A～7A　The IC can be controlled.

2. Vin=18.5V～19.9V Vout=17.1V 0A～2.5A　The IC can be controlled.

3. Vin=18.5V～19.9V Vout=17.1V 4A～7A　The IC can't be controlled.

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PCB.pdf