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LM5116: LM5116 layout and schematic check

Victor Chen_HK
Expert 5130 points
Part Number: LM5116

Hello,

Could you help to check below schematic and layout?

Input 54V-84V, output 36V 8A, switching frequency 200kHz.

DCDC300W84V to 36V.zip

Thanks and best regards,

Victor

  • 0
    TI__Mastermind 40040 points

    lm5116 Flour Plan.pdfHi Victor,

    The schematic looks ok.  I would make a few adjustments.

    1. Change R14 from 750k to  150k

    2. Change Rsense from 10mR to 5mR.

    3. Change R12 from 3.6k to 400k

    4. Change C17 from 100nF to 1nF.

    I checked your layout , I would consider looking at the attachment and follow the guideline stated therein.

    Hope this helps?

    Kind regards

  • 0 in reply to David Baba
    TI__Expert 5130 points

    Hi David,

    Customer has modify the circuit and re-layout the PCB. The DC/DC can operate normally now.

    Below are the Vgs waveform of low side FET. The undershoot at turn-off is about -7V. Will it cause any problem?

    The update circuit and layout as following.

    LM5116.zip

    Thanks,

    Victor

  • 0 in reply to Victor Chen_HK
    TI__Mastermind 40040 points

    When making the measuring you need to ensure you have a very short ground lead on the scope probe.  I recommend a spring clip and kelvin connect to the Gate and the Source of the FET.  if you are using Rsense the ground needs to go to the ground side of the Sense resistor.  But the loop needs to be very small, otherwise you will have noise pick up on the Ground lead. 

     

  • 0 in reply to David Baba
    TI__Expert 5130 points

    The measurement method was correct. Below are the SW waveform showing very high over shoot at high-side MOSFET turn on.

    Any suggestion on the circuit? Besides, currently customer is using 2 layer PCB, will it be necessary to change to 4?

    Best regards,

    Victor

  • 0 in reply to Victor Chen_HK
    TI__Prodigy 700 points

    Hi Victor,

    the switch node measurements shows significant switch node ringing. If you zoom into the rising edge then you will see more clear the ringing amplitude and frequency.

    To reduce switch node ringing: Attached are 3 slides that will help with switch node ringingSwitchnode Ringing.pdf.

    1. Reduce parasitic dI/dt loop inductance of the Power FETs.

    -> place a small (e.g. 0402 size) high frequency ceramic capacitor e.g. 0.047uF between PVIN and PGND close to the Hi- and Low-side FET.

    -> the loop inductance can be further reduced by placing copper layer as close as possible under the parasitic loop area. for example in mid-layer 2 best would be 6mil distance. So yes, using a 4 layer PCB can reduce the parasitic loop inductance.

    -> when multiple power FETs are used like in this case place multiple high frequency caps so each parasitic loop can be reduced.

    2. As the last step is optimizing the snubber filter.

    Best Regards,

    Robert Loke