Over Current Protection

1A_10 Channels.pptxHello,

please check the attached circuit diagram and let me know for further assistance.

Regards

Hello,

Please refer to datasheet page 16. The formula relating external limiting resistor RcL, load current IOUT and current ratio KcL: RcL = VcL(th) x KcL/IOUT.

The highest variation is from current ratio KcL and KcL = KcL(typ) x (1 + dKcL/KcL(typ)). dKcL/KcL(typ) is the accuracy and it is +/-15% at 1A load current.

For making sure the load current does not hit the current limit during normal operation, RcL should be calculated with the lowest current ratio accuracy.

That means RcL = VcL(th) x KcL(typ) x (1 + dKcL/KcL(typ))/IOUT.

At 1A load current, RcL = 0.8V x 2500 x (1 - 0.15)/1A = 1700 Ohms

Regards

Hello,

I do not see the actual circuit. In order to help we need schismatics at device level and details about your observation.

Regards

Hello Verma,

You sent my drawing and I was hoping to receive your schematics and data from lab measurement. You have to check the following once you build the circuit:

1- Make sure the pins are connected correctly

2- After you power up the circuit, make sure the voltages are present

3- Make sure the input pins INx are high for enabling the channels

Regards

Hello,

the circuit looks OK and should function correctly in term of power delivery and over current protection. With current limit resistor of 1.8K, the typical current limit is 0.8V x 2500/1.8K = 1.11A.

The short circuit current limit can be between 0.94A and 1.277A due to 15% tolerance.

The device max power dissipation is 4 x 200mOhm x 1.277^2 = 1.3W.

The current limit resistor max power dissipation is Vcl(H)^2/Rcl = 6.5V^2/1.8K = 23.5mW. There is no need for 0.5W power rating for limiting resistor. 

If the limiting resistor is getting hot, can be from:

1- Lower resistor value

2- Higher voltage on CL pin and in this case the device may be damaged

Could you please double check the Rcl value and measure the voltage on CL pin? Is the power pad soldered to system ground?

Regards

Hello,

In your design the enable pin IN is not toggled. The over current trip is based on analog loop and pulls the FET gate low once the current hits the current limit and puts the FET in saturation region. When the over current is removed, the current loop suppose to release the FET gate and puts the FET in linear mode. Because it is an analog loop, the FET will go back to linear region only if the IN is toggled or the load current goes much lower value than the over current limit. 

We recently changed the datasheet and added this sentence: "External current limit accuracy is only applicable to overload conditions greater than 1.5X the current limit setting"

The upper limit for this design should be 1.5 x 1A = 1.5A and with 15% accuracy the upper current limit is 1.15 x 1.5 = 1.725A. The external current limit resistor value should be 0.8V x 2500/1.725A = 1.159K.

Because the enable IN is not toggled, the solution is to lower the external current limiting resistor from 1.8K to 1.2K

Regards,

Current limit block diagram.pptxPlease use my previous explanation for this design and circuit diagram is attached.