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LMR23630: Input bulk Capacitor

Pradeep Mohan
Intellectual 725 points
Part Number: LMR23630

Hello TI,

we are using the LMR23630A to power a GSM module. 

Our layer structure is as follows

Signal+GND pour

GND

VCC

Signal+GND pour

The datasheet mentions that when the vin source is more than 5cm away from the LMR23630A, bulk capacitance maybe required.

The Vin trace is 0.8mm wide and nearly 12cm long. This trace exists is the third plane (VCC) From here I use vias to connect to the top plane where the Vin is a polygon.

The 12cm trace has an inductance around 220nH from a web based calculator.

How do I decide if I really do need the bulk capacitance.

1. The module is supplied by an automotive battery, taking into account capacitance derating and safety, I think we need at least 50V rated capacitor. The biggest question I have is, can I go with aluminium electroytic capacitors or should I rather go for the polymer based ones (OSCON etc)

2. The bulk capacitance is not used for bypassing high frequency ripples. So should the common guideline of keeping the return loop path as short as possible apply for the bulk capacitance too? Or is it ok to position the bulk capacitance as the layout permits? Or should I stick to the EVM layout?

  • 0
    TI__Genius 11085 points
    Hi Mohan,

    The purpose of the buck capacitor is to use the parasitic resistance ESR to damp the ringing due the the parasitic inductance of the input wire/trace. With 12cm long input trace, 0.8mm width is too narrow. I would recommend increase the width of this trace a lot more, to reduce the parasitic resistance and inductance, and help heat dissipation. Wide and short traces should be used for all traces where high current flows, as much as possible.

    Back to the topic, I think you should have a buck cap because 12cm is long. OSCON is ok if DCR is enough. If not enough, you can also put a small resistor in series with the OSCON cap to add artificial DCR. We typically put electrolytic caps on evms.

    For the location of the bulk, it is not as critical as the ceramic high frequency bypass caps. it can be further out. But you don't want it to be too far away from the input pin, otherwise there's more parasitic inductance between the bulk and input pins.

    Regards,

    Yang
  • 0 in reply to YangZhang
    Intellectual 725 points

    Hello Yang,

    thank you very much for your input.

    The maximum current in the worst case scenario that we have measured is 200mA at 12V. Assuming a temperature rise of 10 degrees, that's around 0.9mm How much wider do you recommend the trace be?

    How do I determine how much DCR is required? I think we will also stick with electrolytic capacitor. 

    Please find below the layout for the 12V -> 3.8V LMR23630A. Here I'm using a Panasonic case G aluminium electrolyte Cap. Highlighted is the Vin polygon pour on the top plane as well as the 0.8mm trace on the inner layer.

    Is there anything more I can optimize with regard to the input capacitors? If the return path for the current through the electrolytic capacitor is not as critical as that for the ceramic bypass capacitor then I can leave the cap as it is. 

    For reference we use the following stackup

    Layer 1 Signal + GND pour (red here)

    Layer 2 GND

    Layer 3 VCC shown in yellow, this layer is used to route Vin to both DC DC convertors on this board, as well as for the multiple voltages used by various ICs)

    Layer 4 signal + GND pour (also used to route the feedback trace)

    Thank you once again for the constant and really helpful support!

  • 0 in reply to Pradeep Mohan
    TI__Genius 11085 points
    I don't think you have to widen the trace width. But I would increase the trace width to reduce the temperature rise and parasitic inductance. It seems you have enough room on layer 3.

    If you have a eletrolytic cap there, you should be ok. I don't think you need additional DCR with that.

    The location of the eletrolytic cap looks ok as well.