TLV62568: TLV62568

ANURAJ NK

Intellectual 510 points

Part Number: TLV62568

Hi,

I could see a parameter called power good delay in TLV62568 datasheet.

Is this the time taken for Power good MOSFET to ON when output is 90% . If not, Can you tell me what is that means?

Regards

Anuraj NK

over 6 years ago

0 Emmanuel Granatello over 6 years ago

TI__Expert 3465 points

Hello Anuraj,

Thanks for your inquire.

You are correct. The power good delay is the time between the following events:

-Vfb falling from nominal value to the 90% of this one

-power good mosfet gets turned on

0 ANURAJ NK over 6 years ago in reply to Emmanuel Granatello

Intellectual 510 points

Thanks Emmanuel for your quick replay.

0 ANURAJ NK over 6 years ago in reply to Emmanuel Granatello

Intellectual 510 points

This delay can be measured between EN signal (high to low since it is Vfb falling) and PG pin (low to high) ?

Will probe the Enable pin and PG pin, measure the time interval from EN low to PG signal High.

0 Emmanuel Granatello over 6 years ago in reply to ANURAJ NK

TI__Expert 3465 points

Hello Anuraj,

the 40us delay does just refer to the Vout. From the EN pin falling edge, you will have an additional delay which is not specified in the datasheet.

0 ANURAJ NK over 6 years ago in reply to Emmanuel Granatello

Intellectual 510 points

So the measuring points for power good delay is feed back and power good pin. Please confirm.

0 Emmanuel Granatello over 6 years ago in reply to ANURAJ NK

TI__Expert 3465 points

Yes Anuraj,
that is correct!

If you ave further questions, please do not hesitate to ask. You will be welcome!

0 ANURAJ NK over 6 years ago in reply to Emmanuel Granatello

Intellectual 510 points

Sure Emmanuel. Thanks for your support

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Power management

Power management forum

TLV62568: TLV62568