Other Parts Discussed in Thread: UCC29002
Hello guys.
One of our customers is evaluating UCC39002. According to their report, it seems that the plus input voltage of Adjust AMP in the function block diagram is pulled up to 3V by high side NMOS controlled by Start Up and Adjust Logic block when the system output current is about zero because ADJ terminal sinks about 6mA with 0V EAO terminal voltage. Also the ADJ sink current is reduced when the system output current is about 2A (the sense resistor between CS+ and CS- is 1.25mohm).
So could you please tell me when the high side NMOS controlled by Start Up and Adjust Logic block is turned off after UCC39002 enabled by powered up?
Your reply would be appreciated.
Best regards,
Kazuya Nakai.