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SM72295: SM72295: More Questions about SM72295 Implementation and Design Review

Nicholas Ipri
Expert 1010 points
Part Number: SM72295
Other Parts Discussed in Thread: INA213, TIDA-00120, , CSD18502Q5B

Pasting this in from the prior thread

Hi Jeff:

I cant access the questions on the schematic. Perhaps you can post them in another way.

Your timing diagram was very helpful. Hopefully, TI will include it in a future rev of the 72295 datasheet

I attached scope shots of the LI and HI signals I now have. Going from top to bottom... HIA, LIA, HIB, LIB.

The top shot is a 50% duty cycle, the bottom is 80%.

The ringing in the traces is due to less-than-ideal scope probe grounding,

  • 0
    TI__Genius 12990 points

    Hi Nicholas,

    Thanks for the update. It doesnt look like HOA/HOB are 180deg separated and not completely interleaved for 2 phase. I went ahead and included the schematic review in a screenshot below. I also put the SM72295EVM on the bench and verified that powercycling VCC with VDD still present does not affect the part while not switching. While switching the HO/LO output behave as expected from HB-HS UVLO having HO shut off before LO due to the lower threshold.  As we Discussed, either we can create a new thread or I can post in this one about minimum bootstrap charge time and deadtime input Jef feasibility for this application.  If we dont post a new thread I will simply reply back to this thread within 24-48 hrs.

    Thanks,

    Jeff

     

  • 0 in reply to Jeffrey Mueller
    Expert 1010 points
    Thanks, Jeff:

    >>It doesn't look like HOA/HOB are 180deg separated and not completely interleaved for 2 phase. <<

    They are , but only at 50% DC. The timer I am using isn't going to let me change the phase of the signals. Ideally, I would want to shift the phase of HIB and LIB (the lower 2 traces) to be 180 deg out of phase with HIA and LIA. How critical is this for proper circuit operation? I should be able to achieve the phase shift if I use 2 separate timers as opposed the one I use now but that wouldrequire a respin of the board

    We intended to "design in" the option of using the internal current sense amps but decided to continue using the INA213. We will likely respin the board and implement your suggestions.

    BTW, I created this particular thread new this morning. Should I create a new one?
  • 0 in reply to Nicholas Ipri
    TI__Genius 12990 points
    Hi Nicholas,

    Sorry about that I didnt realize this was the new thread, we can stay in this one.
    If you need support designing in the current sense amps, feel free to reach out again.

    The current circuit operation is ok however its important to pay attention to ripple current heating effects with the battery. Since the point of interleaving is to reduce ripple.

    For the deadtime - its still recommended to not shape the input signal and if you do make sure the signal is not over shaped as to not be attempting a large deadtime. LI DT is 150ns and HI DT is 60ns which is only 3% of the switching frequency and 5-10x larger than rise/fall times. Looking at TIDA-00120 reveals that the circuit has the same 560/220pF on LI/HI however the 270 ohms are not added therefore the RC time constant is lower and so is the deadtime. I have contacted the designer for this TIDA and hope to update you with an answer asap focusing on if this deadtime approach should be done, and with 270 ohms.

    Did your other concern have more to do with minimum ON time of LO in order to recharge the bootstrap?
    or maximum ON time of HO to deplete the bootstrap below HB-HS UVLO or your systems required HB ripple?

    Thanks,
  • 0 in reply to Jeffrey Mueller
    Expert 1010 points

    Thanks, Jeff

    >>If you need support designing in the current sense amps, feel free to reach out again<<

    The layout is optimized to use the INA213 so we will likely stick with them. They also have very good input offset voltage spec.

    >>For the deadtime - its still recommended to not shape the input signal and if you do make sure the signal is not over shaped as to not be attempting a large deadtime.<<

    We find that we are getting much better results when we remove the capacitors (C23 - C26) from the input signals. I think that those RC networks, in conjunction with the programmable dead time I am able to introduce between the complementary signals, was hurting us. I still have a minute amount of dead time programmed in that is producing about 100nS of deadtime between HI and LI. What I originally though was a deadtime issue was apparently an issue of an excessively high DC on the lower MOSFETS (as we discussed), which also causes shorting issues. I am planning to leave in the 270 ohm resistors though (R28 - R31) as these probably help to preserve signal integrity / decrease ringing.

    >>. I have contacted the designer for this TIDA and hope to update you with an answer asap focusing on if this deadtime approach should be done, and with 270 ohms.<<

    It would be interesting to see what he / she has to say about this. Since I can control my deadtime through software this is probably sufficient. I wish I could control phase between the timer channels as easily! I have a question in to ST about that.

    >>Did your other concern have more to do with minimum ON time of LO in order to recharge the bootstrap?
    or maximum ON time of HO to deplete the bootstrap below HB-HS UVLO or your systems required HB ripple?<<

    My big concern here is how to determine the minimum on time of LO to recharge the bootstrap cap. (or, to look at it another way, how to determine  the maximum ON time of LO before shorting occurs from V_OUT to GND through the LO MOSFET and inductor) I've sort of determined this empirically but I would like to understand it better from a theoretical standpoint.

  • 0 in reply to Nicholas Ipri
    TI__Genius 12990 points
    Hi Nicholas,

    Sorry for the late reply.
    After talking to the designers it seems that there was a problem in generating dead-time on both the edges using MSP430. In this design, there was no other simple way of getting the required dead time. Therefore, we depend upon the RC time delay and the Vth of SM72295 to get the required dead time. So the RC value has to be maintained as specified in the schematic. Any additional input resistance will create extra delay that will be detrimental to the operation of the circuit. If the uC has no way to set dead time, a pure capacitance filter might work if the devices driving the HI and LI have skewed drive strength (sink current>source current), since the dead-time is dependent on those parameters.

    For minimum LO on time – there is very little usable material online. In general, the charge needed to turn HO on (total gate charge) has to be delivered into Cboot during the minimum LO on time. The following factors affect this include:
    1) The speed of the boot diode, forward recovery time especially.
    2) The value of the current limiting resistor, Rboot (not used).
    3) The inductance of the current loop from CVCC to Cboot and back (PCB layout) since charging the bootstrap is a high frequency process.

    The first step to take to find this out is to determine your minimum Cboot needed to keep HO on and HB-HS UVLO OFF. Cboot = (Qg_total)/(V_HB-HS_UVLO) or 0.47uF. Since Your FET, csd18502q5b, has a total gate charge of ~82nC@12V so this charge has to be supplied from Cboot each time the MOSFET is turned on. In the steady state this is also the charge that has to be put back into Cboot from Cvcc.

    You should charge the MOSFET gate to at least 10V, so let’s assume that this is the voltage on Cboot when LO is turned on. The voltage change on Cboot is Qg_tot/Cboot or 82nC/0.47uF or 0.174V -> we need to at least charge Cboot to 10.174V to turn on HO again. Assuming a 1V drop on Dboot and since there is no Rboot then from 12VCC there is about 2V available to initially charge Cboot with. The amount of time it takes a cap to charge from 10V to 10.174V with a 12V supply can be seen with the equation for voltage across a capacitor with time:
    Vcap = Vsupply + (Vo – Vsupply) e^-t/Rboot*C_boot
    Solving for t yields:
    t=- Rboot*C_boot*ln(Vcap-Vsupply/(Vo-Vsupply)
    Where Vo=10V, Vcap=10.174V, Vsupply=12V, Rboot=1 (for simplicity) and Cboot=0.47uF

    This equation yields ~43ns to charge Cboot from 10V to 10.174V from a 12V supply with a time constant of 0.47us
    Note: The smaller the Cboot the longer it takes to recharge which is counter-intuitive because the smaller the cap the faster the cap discharges its current into the FET and therefore looses its voltage faster as well.

    The main thing you will need to think about is what duty cycle the power stage needs in order to provide the input / output conversion ratio you want. This will set Dmin for you. Leaving you to make sure Cboot can be replenished in the available time.

    Please let me know if this answers your question.
    Thanks,
  • 0 in reply to Jeffrey Mueller
    TI__Genius 12990 points

    Hi Nicholas,

    Just checking to see if you had any more questions or concerns with SM72295?

    If not, and this thread was resolved to your satisfaction, please click the green button.

    Thanks!