TINA/Spice/UCC28C42: ucc28c42

Pete: thnx a lot for putting the effort to simulate. Appreciate.

Yes, I noticed that & I tried to do various circuits to buffer with higher amplitudes.

It does not seem to matter!

HOWEVER: one thing for sure  matters which is NOT reported anywhere.

That is the ramp at CS MUST have a slightly negative value.

I used many opamps to do this: but the problem is they all seem to add a + value at the low end. This wont work. 

You seem to be saying if I get amplitude of approx 1V , one can get v/m, ...just that I have to find a way to get a ramp , say, -.25V to 1.25V...??

I will try some more tricks. 

Peter

Pl see attached file: I have a ramp of amplitude as expected. With negative being several hundred mV

I do not think it is still "working" in correct voltage mode. I do not want to change compensation circuit yet.

I changed amplitude to several values, no matter.

In order to double check thinking flyback may cause v/m issues, I used it for my proprietary converter, of  course it wont "work" as expected!

So, I would need your help in selecting another model ..I do not know which other cm/vm controller TINA-TI has or perhaps you will find the root cause of this & help us all fix it.

thnxUCC28C42_3xSTEADY3rd.TSC

Peter:

Pl see the ppt file: it explains why the scheme of "just apply a ramp-- in particular a scaled  RTCT ramp from the timing pin back at the CS pin" is in conflict with the gate dr pulse timing in the chip.

You notice that the gate pulse begins as the RTCT ramp value ramps down to 0

In current mode, the current sense signal is causal- meaning, current sense signal begins BECAUSE THE GATE DRIVE has gone high & turned on a switch which begins to conduct. As the current rises, CS signal rises. At some point, AFTER THE RAMP BEGINS TO SLEW UP, this hits the scaled values of COMP signal in the internal comparator ending the gate pulse.

If the RTCT ramp is scaled/buffered & applied at the CS pin, the same signal beings the  gate drive pulse while CS signal now is already almost at its peak(there is some delay in buffering/scaling). This creates a very fixed short pulse. In other words, the gate pulse has almost 99% ON time. The second plot  gives you this timing.

vm_operation_conflict.pptx

What confuses me is that for decades all published work casually mentions this  easy conversion of CM to VM!

To be in voltage mode, the COMP signal must be within the range of the ramp!( see Andreyssak)- so that its moving up & down  varies the time when the gate pulse ends as the slewing ramp hits it. In either of the cases, the gate pulse starts up at the beginning of the ramp.

Yes, I know the buffering created the delay. Yet  the issue remains.

But your idea is very appealing : I am going to try it up. 

Thnx Peter

robin

I think there are  some issues with having 2N2222A to get a ramp scaled so that it can be connected to CS pin. I am not using my own power stage at all in this case. We are trying to make the voltage mode work with the example power stage given for UCC28c42.

Pl  run the attached file & see the  ramp from the output of the ac coupled 2N2222A stage: notice that the amplitude of the ramp varies widely. Even though there are times when the ramp value is almost the same as the value occurring due to Rcs,  Vrmp in my simulation elsewhere  goes down to very low values. I think this is the reason the circuit with ramp added at CS pin does not work properly.

Notice also that Rcs is almost half the value given in the Example file: yet it works with much lower value of V(rcs). It works over a wide range of values of Rcs.

So this is very puzzling.  Meaning, the ramp from 2N2222A also ought to work over a wide range of values. 

Even when the 2N2222A ramp may have the same value as the V(Rcs) over many cycles, if you connected that  to the CS pin, it wont generate correct pulse width at all.

I have explored lots of values around the 2N22222A circuit, but none "works".

I would really really appreciate help in making the voltage mode work for UCC28C42 chip!

Help!

robinUCC28C42_npn2.TSC

UCC28C42_633.TSCIt is perhaps easier to manipulate the buffering of the UCC28c42 ramp using a "buffer" than a 2N2222a. Pl see attached circuit using OPA633 buffer model-: it reproduces a buffered ramp very similar to voltage from RCS(Vcs). There is no delay. So the RTCT ramp start coincides with the buffered ramp( a neg value). Then around the time the pulse width happens around 400usec later due to V(rcs) value, the buffered ramp has almost same value. YET, this wont create proper operation of the UCC28c42 if connected to the CS pin.

This is very puzzling.

Can you all help me fix this?

UCC28C42_633_2.TSCI do not know how the previous file using OPA0633 will work in your system. Attached is another one: as I said, the signal at vrmp has all the properties one expects for the ramp to be sent to CS pin if UCC28C42 is to run in voltage mode. It does not. This version wont even generate  gate drive pulses.  What am I doing wrong here?

Peter

I am wondering if you have  any file someone made  to work in v/m using UCC28C4x?

All my efforts---hundreds-- have failed to produce a PWM out of ramp fed back at CS pin. On the other hand, there is a wide range of Rcs values that will always make it work in current mode!

Attached is my last file: a buffer OPA063 gives a lot of freedom in making any ramp out of RTCT pin- much better than 2N22222A. 

BTW: I also failed to produce ANY meaningful operation by attaching a voltage at COMP pin.

The model does not operate meaningfully .

Let me know if I have other options to model a v/m loop.

thnxUCC28C42_633rev.TSC

robin