LM5066: Can multiple LM5066s get paralleled up

Nick,

The ST FET is really good for SOA, but not so good on Rdson.  Cold start may be ok but if you power cycle and start with the FET hot, the SOA inputs are derated for starting die temp vs max DS operation temp.  This is where the paralleling helps, to keep initial temp down.  Correct statement of one FET sees the SOA stress due to Vth, Vplateau differences. During fault (power into short) you will still have gate timing differences along with insertion time differences.  Putting 2 x LM5066 in parallel will not be a 100% fix as insertion time and start up timing (gate source current, timer current, FET Vgsth/plateau) still will come into play.  20mF is a lot of cap to start into.  You will most likely need to use dv/dt start up control with Cgate that also places start up SOA on a single FET.  I would focus on reducing load cap by using better polymer caps (lower C, better esr).  Use the design calculator tool located on the product page for download to assist.

Brian

Brian,

Unfortunately I cannot decrease the load caps. Those load caps are the bulk input to the switchers post LM5066. Unfortunately those switchers have to provide a very large current step load while simultaneously maintaining the output to a very very tight tolerance.

Also, my application is not hot pluggable. It is at the end of a large and long cable. My primary use for the LM5066 is for controlled charge of the caps, and for power monitoring purposes.

While I agree that 2x LM5066 in parallel is not 100%, given the FET differences. But if the UVLO, OVLO, and Timer pins are tied together, couldn't they operate close enough to spread the SOA "pain" with a power limiting start? One would have to calculate the timer cap using twice the current, as you now have two current sources feeding the cap, but that should be trivial (unless there are other unknown gotchas, which is why I am here).

I will download the spreadsheet tool and use that to verify what I have calculated so far.

It is too bad that the dv/dt mode is not fully explained in the datasheet for the LM5066. It is only mentioned in one dashed box in a typical application figure. Is there any documentation which covers the theory of operation with the additional dv/dt circuit? Calculators a nice to get an answer, but I like to know why my circuit works the way it does. It is ussually helpful in debugging.

Which ST FET are you referring to? The SUM70060E I have been planing to use so far is a Vishay device. I am always open to other options.

Thanks,

Nick

Nick,

The calc tool has a dv/dt section (product page or www.ti.com/hotswap). The circuit is just a gate cap that dominates the source current rather than use Crss+Ciss/Crss/Crss+Ciss of the FETs for control. It prevents power up into Power Limit mode, which with the amount of cap you have would most likely cause SOA failure. dv/dt still passes the same energy through the FET (same as 1/2 CV^2 of the output cap bank) but over longer time, allowing heat transfer to the FET case away from the die. My error on the ST comment. Was from memory. Familier with the part # and its basic characterisitics, got wrong manufacturer from memory bank.

Have not tied timer pins together before. Sounds like it may work, but check with 2 x EVMs 1st. overcoming gate current and Cgate (dv_dt) is probably still a stopper.

Brian