Hi
I read the datasheet. There are some behavior what I do not understand.
If the current reached the current limit,this device just report by CS pin the current is reached. However this device does not turned off (channel off) if Tj is under Tsd.
Is my understanding correct?
On the other hand, it is described on the datasheet there is a case of channel off state.
What is the conditions this device is turned off(=channel off)?
Best Regards,
Koji Hamamoto
Your understanding is correct. The device regulates the current limit at the set value and the FET is in saturation region. The OUTPUT still delivering the regulated current as long as the junction temperature is below Tsd. Reaching the Tds depends on supply voltage, current limit set and ambient temperature.
The FET turns off momentary in case of hard short to GND due to fast loop of 1uS response time. After the momentary turn off the FET comes back on automatically and regulates the current at the current limit set. Attached pictures shows the behavior in case of over load and hard short.
Scope channels CH1 = VOUT, CH2 = CS signal and CH4 = laod current
Regards
Hi Mohmoud-san,
Thank you for your support. I would like to ask more detail to understand the behavior of this device.
Q1: Regarding the waveform you posted above;
The left side waveform is in case of "hard short" ? And The right side waveform is in case of "over load"?
If it so,(at the right side waveform) Vout was turned off because of thermal shutdown? It looks the Vout turnd off because of the current limit.
Q2: I measured TPS1H100-Q1 with TI-EVM. I saw the turned off behavior after the current is reached to the limit. Is this the thermal shutdown as well?
What we would like to know is how much delay time until turn off Vout it will take after the current is reached to the current limit .
If VOUT does not turnd off even though the current is reached to limit(Tj < Tsd), we can not estimate the delay time. Is my understanding correct?
Best Regards,
Koji Hamamoto
