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Hello, I tried to measure Irr of DUT, So I made circuit using LM5114
Almost of circuit is soldered.
And this is example of Irr test circuit
Outline
1. ATMEGA8A makes 10us pulse 2 time (It will be more shorter if this circuit works)
2. LM5114B receive signal and controls the gate of IRFP250
3. When first waveform reach to the gate of IRFP250, it passes current through 70uH -> IRFP250
4. While gate is turned off, current in Inductor pass through DUT forward side.
5. And the second waveform reach to the gate of IRFP250, DUT makes reverse current instant.
Meausrement Result
1. OSC1 : Idd(10V), OSC2 : OC1A
First waveform reach 650mA. Not high as expected, and second wave is unsatisfied ( maybe due to 0.1Ω )
2. OSC1 : Idut, OSC2 : OC1A
Yes, 550mA passed through DUT forward position
3. OSC1 : Idut, OSC2 : OC1A
What is that? Rising founded on Irr curve? Something went wrong.
Measurement Equipment
Source : Keithley 2636B, Keithley 2651A
Oscilloscope : DPO2012B(100MHz)
OSC Probe I have : TPP0200 Passive Probe (Default, 200MHz), TCP2020 Current Probe (>50MHz), Active Probe
Defect I can guess
0. Board : I'm not using PCB currently. It is on Perfboard and there is many parastic capacitors on each copper hole - but not sure how much effect on the test.
If I fix some defects and sure i can test Irr, I'm going to make PCB
1. Probe : I also want to use 'shunt regulator' to measure Irr, but i cannot trust voltage accuracy of Passive Probe.
If i use proper probe, then long-wire can be deleted on circuit.
Active probe support under 7V, so it is not suitable for measurement.
2. Long wire : As I said, due to current probe. Is this make Lloop?
3. Equipment : Maybe 2651A limit output current...? I set its limit to 5A now.
4. 0.1Ω : to limit Idd(10V). According to Example Circuit - there is no resistor on FET.
Hi DHL,
welcome to e2e!!! thanks for asking about LM5114, Im an apps eng and will help.
Can you please tell me What application is this???
whats the peak current of your application?
Is this a laser diode?
whats the long tail on the second waveform Idut?.. I suspect the dut is being pulled to ground like normal in the first waveform.
When you probe make sure you are using the pig tail technique with small ground leads for low loop inductance and cleaner waveforms.
also if you can connect the "long wire short" closer to the driver VSS pin if possible this will make gnd bounce and corrupt the input signals.
is the driver or fet damaged?
Thanks,