TPS568215: MIN/MAX value of low side negative current limit value

Hi Oba,

Unfortunately we don't have the data. Please note that the inductance will also has 20% variance typically.

For the minimum inductance for the IC, you should consider more than the negative current limit. With small inductance, current ripple will be bigger, and you need bigger output capacitor to have proper output ripple. The efficiency is lower due to bigger RMS inductor current. The peak current will also be bigger, and peak current limit needs to be considered. What's your maximum output current by the way? Also, to ensure loop stability, the L*C you chosen should be within the limit of recommended L*C range, which is 1.2u*100u to 1.2u*500u in your case.

May I know why you want to use such a small inductor?

Hi Neal

Thanks for your reply.

The maximum current is about 4A.

I would like to use smaller inductor to expect faster response.

Regarding L*C requirement, could you tell me more technical background of this requirement?

Is there any formula to calculate that value?

 

Regards,

Oba

Hi Oba,
The formula is introduced in section 7.3.1 in datasheet. the LC double pole is calculated as Equation 1. In your case you can use small inductor and big output capacitor, let the L*C to be close to 1.2u*500u, to get the best load transient performance.
For the minimum L, I suggsest you use 3A as negative current limit to calculate, then take 50% margin due to the variance of Inductor value and IC negative current limit

Hi

Thanks for your reply. And I'm sorry for my late response. I needed some time to understand your answer, especially section 7.3.1 in the datasheet.
I'm still struggling to understand technical background.

I read section 7.3.1 in the datasheet. 

According to this section, the control loop seems to have LC double pole and ripple injection zero.

And ripple injection zero position depends on the switching frequency.

The LC double pole should be close enough to this ripple injection zero to maybe keep phase delay to be around 90 degree till zero cross( I’m not sure where is zero cross actually…)

 

On the other hand, regarding table 5 of 8.2.2.1.4, I have some questions.

 

1.

Why are all Cout(MAX) 500uF except for 5.5V/1200KHz case?

Where does this value come from? I feel this doesn’t come from control loop theory written at 7.3.1.

 

2.

Why are Cout(MIN) 88uF for many case?

Where does this value come from? I feel this doesn’t come from control loop theory written at 7.3.1.

 

3.

I understand double pole location of all these LC values in table 5 is not so far from ripple injection zero.

But I can’t understand where these range come from. Could you tell me more detail how to think about this range?

 

Regards,
Oba

Hi Oba,
Good question! Actually we have done bench test on parameters in this table , but it doesn't mean if you use a bigger Cout, it will bring problems. when we do validation, we just cover customer common parameter selections. Regarding to your special design, I would say bench test is needed to check whether there's problem or not.

OK, I understand the value in the table come from our bench test validation.

It is not limit but we validated It works with the L and C in the table at least.

So if L*C we chosen is within the range of L*C \in the table, it would be safe in theory.

This is my understanding. Correct?

 

Isn’t theoretical limit value for L*C and each L and C available?

There is basic theory in 7.3.1, but it doesn’t tell actual limit value.

 

Regards,

Oba

Hi Oba,
Yes your understanding is correct.
For the loop theory discussed in 7.3.1, yes it's just basic theory to give you an idea about how we recommend proper L*C. By using the principle "The inductor and capacitor selected for the output filter must be such that the double pole is located close enough to
the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase margin for the stability requirement.", we can get a start value of L*C. As you know, for the phase margin, some customers need >50 degree, but some customers think >35 degree is enough for their application. So we give out the ''recommendation' rather than a strict "limit" for normal application situation.

Hello,

 

Thanks. I have still some questions.

 

1.

So when using L and C from the table, how much phase margin they have?

 

2.

Is it impossible to tell more detail about 7.3.1 theory to calculate phase margin in each case ?

As I mentioned before, it shows only basic concept and doesn’t show so detail like DC gain.

We can’t calculate or simulate for each customizing cases. Also we need to think about capacitance value drift like aging etc.

 

3.

Is there any other special limitation for L and C choosing except for sink current limit and this control loop.

 

Regards,

Oba