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Hi Skate,
The bq76200 does not have a maximum number of FETs, but while you can scale the CVDDCP capacitance to provide more charge into the FET gates, the resistance in the internal driver paths is fixed. Eventually you can add enough FETs that the switching is too slow to be safe for the FETs or for the pin voltages to change without collapsing the VDDCP to the UVLO threshold. It sounds like you may have reached that value. You might check your calculations on the CVDDCP size and check to see if the resistance from the DSG and CHG to the FET gate is optimized. If it is a new design, be sure the Cpack is not unexpectedly large.
Hi Skate,
10 uF sounds quite capable. See the data sheet section 8.1.1.3 for the recommended ratio (23.5). You might look at the circuits and results in www.ti.com/.../slva729 and www.ti.com/.../slua794. If you have had the board/design working with 12 parallel FETs but not 14, you have likely reached the physical limit of the circuit due to the internal resistance of the IC.
