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BQ40Z60: DSG FET protection cannot be cut off, causing MOS FET to burn out (CHG & DSG FET independent path design )

JANSON CHEN
Prodigy 250 points
Part Number: BQ40Z60
Other Parts Discussed in Thread: CSD16407Q5, CSD17308Q3

HI,

Currently designing a 50A output product using the Bq40z60, considering space and cost issues,
Adopted the CHG & DSG FET independent path design (please refer to the attached circuit)

When the discharge protection test was performed, the DSG FET could not be completely cut off quickly, causing the MOS FET to burn out.

Analysis of the DSG FET Gate waveform and found that VGS still has residual voltage (about 1.7V) after the truncation. This is enough for the MOS FET to turn on again (please refer to the following waveform)

My suspicion is that the Bq40z60 has special requirements for the selection of DSG MOS, or that the current of Sink low is too small.

Do you have a design proposal for CHG & DSG FET independent paths or a better way to solve the problem of truncating DSG FETs? (If there is an external driver solution is better)

Janson

BQ40Z60 Circuit.pdf

  • 0
    TI__Mastermind 42535 points
    Hi,

    Your thread has been assigned to me. Please expect an answer in 5 working days or less.
  • 0 in reply to Batt
    Prodigy 250 points
    HI,Batt : If you need more information, please let me know.

    Janson
  • 0 in reply to JANSON CHEN
    Prodigy 250 points

    HI,Batt :

    I have performed OCD protection waveforms under several different load conditions.

    It is found that the VGS voltage of the DSG FET turn-off will increase with load conditions.

    Eventually the DSG FET crashed (please refer to the attached file Page1 ~ 4)

    Even trying to replace MOS FETs of different specifications, this situation seems to be more serious (please refer to the attached file Page 5)

    You have better suggestions?

    Janson

    BQ40Z60 DSG FET TEST.rar

  • 0 in reply to JANSON CHEN
    Prodigy 250 points

    HI,Batt : 

    I tried to change the DSG drive circuit (see additional file page1) and confirm the waveform of the Bq40z60 DSG PIN after the protection action is turned off.
    Found a phenomenon, the voltage of VGS does not seem to come from any parasitic capacitance of the MOS FET.
    I set the OCD1&2 protection point to 3.0A and performed the 4.0A, 5.0A, and 6.0A modes. I found that this voltage seems to be sent from the IC and increases with load conditions (see Attachment Page 2-4).
    Attached to this Project's Layout diagram, can you provide suggestions?

    BTW, I have to solve this problem in the shortest time, please provide the best solution as soon as possible.

    Janson

    bq40z60 Modify driver circuit.pptx

  • 0 in reply to JANSON CHEN
    TI__Expert 5090 points
    Hi Janson,

    Can you provide your schematic, so we can look at that more closely? I assume you have a series resistance between the device DSG pin and the DSG FET gate, can you check across that resistor, to see if there may be some IR drop on it? We've seen some cases where an unexpected gate current may appear. I am not as familiar with this device, but I believe during turnoff the DSG pin will pull the pin toward the ACP voltage. If you have some delay circuit on that pin, it may keep it up higher for longer, rather than it following the PACK+ voltage directly.

    Thanks,

    Terry
  • 0 in reply to -Terry
    Prodigy 250 points

    HI,Terry : 

    Thanks for your feedback, you can finally start discussing this issue.
    First, the ACP pin is derived from the 19V voltage (used by the Charger). When the DSG protection test is performed, the 19V voltage has been cut off, and the 19V voltage should not exist.

    In the first post of this post, I have provided the complete design schematic (you can get it in the first attached file)

    In the latest state, I reverted my current PCB configuration to the most basic circuit and still maintained the CHG&DSG split path and used 2 different MOS FETs (CSD17308Q3 & CSD16407Q5) for DSG Gate waveform measurement.

    An interesting phenomenon was found. At the moment of DSG shutdown, the DSG pin of the IC can smoothly pull the voltage down to negative voltage.
    But after about 10uS, the voltage is pulled back to between 1.6V ~ 2V, I can be sure that this will make the DSG FET turn on again.

    In this article I will provide the above test waveforms and schematics again,For actual part specifications or parameters, you can refer to Page1.
    The only difference is the change of the Q5 DSG FET's Parts.

    Urgently expecting the TI team to help me solve this issue.The solution is still going on, and if I have updated information, it will be available in this article.

    Janson

    2018-9-1 test status.pptx

  • 0 in reply to JANSON CHEN
    Prodigy 250 points

    HI. Terry / Batt:

    I further observed the effects of the BMS Chip and Charger mode and DSG Gate waveforms, and found that the Chrager action has absolute influence.

    I tried several modes of testing. (See the attached file charger modetest results),Whether the Gate uses a Diode or a resistor, this voltage will be affected as the Charger is turned on or off.

    These tests may be helpful in analyzing the problem, and attaching the PCB layout of this Project, can you provide suggestions?

    Janson

    4747.CHARGER MODE TEST.pptx6215.bq40z60 PCB Layout.PDF

  • 0 in reply to JANSON CHEN
    Prodigy 250 points

    HI,Batt / Terry :

    I analyzed again to keep or remove the reverse Diode (D4) on the CHG split path and cross-test with Charger ON/OFF.
    Found that the DSG FET VGS voltage still affects the drive signal as the Charge starts. (Generates a small leakage voltage)

    After loop analysis, this is likely to be reversed through the Diode (D4) to somewhere in the loop or IC 
    (See Page 2-3 of the attached)

    This situation will improve when I try to change this Diode to a higher VF material,but will not meet the charging voltage requirements

    When I tried to remove the D4, I compared the results of the charger's ON and OFF operating conditions. When the charger is started, there is still a slight leakage,this tiny drain voltage is improved after the charger is turned off, and the DSG FET can be cut off smoothly.

    (See Page 4-5 of the attached)

    So, I can't determine the interaction between the internal Chrager and the DSG Gate in the Bq40z60.

    Can you provide or confirm this principle?

    Janson

    Charger mode VS reverse Diode(0903).pptx

  • 0 in reply to JANSON CHEN
    Prodigy 250 points

    HI,Ti Team : 

    This issue has not been resolved and can be obtained from another link..

    https://e2e.ti.com/support/power_management/battery_management/f/180/p/724485/2674577#2674577

    Janson

  • 0 in reply to JANSON CHEN
    TI__Mastermind 42535 points
    Janson,

    I'm closing this thread and redirecting to the other thread where you are interacting with Terry.