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TPS659039-Q1: Document on Sequencing

Shinu.V.Mathew
Genius 10530 points
Part Number: TPS659039-Q1
Other Parts Discussed in Thread: DRA75

Hi Team,

One of our customer is using TPS659039-Q1 and need inputs on sequencing.

We gone through the application note http://www.ti.com/lit/an/swca285a/swca285a.pdf but it is listing only 10 rails power sequence. But IC can support  total  7 switching and 11 LDO rails. All these rails were not available in the application note. 

Customer configured device as shown below. 

VCC1=3.3V, BOOT0 & BOOT1 pins are grounded. 

LDOs & SMPS usage screenshots are attached below. Please let know the sequencing required in this config.

TPS659039-Q1.pdf

Regards, Shinu Mathew.

 

  • 0
    TI__Genius 10530 points
    Hi Team,

    This PMIC IC is used to power Infotainment processor DRA75 .

    Regards, Shinu Mathew.
  • 0 in reply to Shinu.V.Mathew
    TI__Genius 16410 points
    Hi Shinu,

    The document you linked is to show the different power-up and power-down mechanisms in the device.

    For part-number-specific configuration settings and sequences, please see the user's guide:
    www.ti.com/.../swcu175

    Regards,
    Karl
  • 0 in reply to Karl Wallinger
    Prodigy 90 points

    Hi Karl,

    We have gone through the application note and was useful.

    Actually we are using this PMIC IC to power DRA75 processor. Kindly help us in below query as well:

    We are trying to understand the PMIC power up sequence, and reset release by PMIC to DRA75 during power up and when DRA75 release the Reset after seeing the power on reset input from PMIC.

     We have connected rstout of DRA75 to NRESWARM pin of PMIC. So with this connection we are confused that PMIC will be continuos RESET state during power up. Because the PMIC has to relese its reset to DRA75, until then reset out of DRA75 to PMIC (NRESWARM) pin will be LOW. Which menas it will be in deadlock reset state.

     

    Please clarify or correct our understanding.

    Else let us know what is the state of NRESWARM pin of PMIC & DRA75 reset out pin during initial power up sequence.

     Please refer attached doc to understand our query.

     PMIC to DRA75 Power Up Sequence.docx

    Thanks in advance.

    Manoj.

  • 0 in reply to MANOJ KUMAR K M
    TI__Genius 16410 points
    Hi Manoj,

    RESET_OUT (PORz in to DRA75) is set high at the end of the sequence, regardless of the state of NRESWARM pin. So there is no deadlock state. After the PMIC completes its power sequence, RESET_OUT will be high. Then after DRA75 initalization, it should set its nRSTOUT pin high, which will set the PMIC's NRESWARM input high.

    Regards,
    Karl