UCC25630-1EVM-291: UCC256302 problem with Leakage inside Trans.

Hi Doi-san,

LL/SS will be discharged if the controller is detecting ZCS operation. If there is a great deal of noise on ISNS, this can create a false ZCS detection. Try populating C30 with ~220pF. Also please share the transformer specification of your custom transformer (Lm, Lr, turns ratio, etc).

The controller look at the lower of LL/SS pin voltage and FBreplica to set the switching thresholds. If LL/SS is pulled low due to ZCS, this will push the LLC to higher switching frequency to get out of the capacitive region. When the switching frequency is pushed higher, this will also reduce the gain of the power stage, resulting in a dip in output voltage.

VCR should always have a common mode voltage of 3V. Please keep the VCR waveform between 0V and 6V.

Best Regards,
Ben Lough

Hi Ben-san,

Customer transformer is now tentative.

Lm = 800uH

Lr = 60uH  = 30uH (leakage) + 30uH (Added outside Inductor )

Np = 48T,   Ns = 3T,  Nc = 4.5T 

Hi Doi-san,

These parameters look fine. Please try populating C30 with ~220pF to see if this addresses the output voltage dropout issue.

Best Regards,
Ben Lough

Hi Ben-san,

In the combination of PFC (UCC 28056) + LLC (UCC 256302)
We are conducting output transient fluctuation test, but the following problem has come up.
Please tell us about improvement measures.
 
<Test condition>
PFC input: AC 100 V
LLC output: sudden change of 12 V 10 A (100%) ⇔ 0 A (0%)
Load device: Electronic load
Load sudden change cycle: 1 Hz duty = 50%
 
<Problems>
At the timing when the load has changed from 100% to 0%, the auxiliary power supply (Vcc) voltage by the LLC auxiliary winding of the evaluation board lowers and the IC operation instantaneously stops.
After the operation is stopped, it restarts with the start circuit, but the 12 V output drops by several volts during this period. In case
This failure phenomenon occurs at a considerable frequency.
In case
<Countermeasure and consideration>
① If 47 μF is added to the capacity of the smoothing capacitor C 16 = 120 μF of Vcc,
The drop in Vcc was alleviated and some effect was recognized,
Although the effect is not 100%, the drop frequency of 12 V output decreases.
 
② However, if this capacity 47 μF is added to the current circuit,
The charging time of the start circuit becomes long, and it is not practical because the starting time from input power on to output rising is over.
 
③ As the output current range that maintains the output stability at present, the lower limit of the spec that can be compromised in sudden load change is around 0.3 A (3%), and it seems that it is necessary to add this dummy resistance.
This will be designed to reverse from energy saving and high efficiency targets.
 
④ Consider setting the burst mode level for the above improvement.
Based on the calculation formula of UCC 256304 Japanese version data sheet 8.2.2.21,
To optimize the programming resistance and investigate whether the problem can be improved,
Perform the following.
   When the voltage (upper limit: 1.86 V lower limit 1.14 V) measured by inserting the resistance 10 KΩ into the emitter of the photocoupler (U 2) was substituted into the calculation formula (75) of the data sheet,
When calculated using IFb = 81 μA of the IC electrical characteristics table,
The VLL value becomes a minus value, and the calculated numerical value has no validity, why?
 
⑤ From the contents of ① to ④ above, good improvement measures can not be seen at present,
Is there a breakthrough plan?

Hi Ben-san,
In the combination of PFC (UCC 28056) + LLC (UCC 256302)
We are conducting output transient fluctuation test, but the following problem has come up.
Please tell us about improvement measures.
 
<Test condition>
PFC input: AC 100 V
LLC output: sudden change of 12 V 10 A (100%) ⇔ 0 A (0%)
Load device: Electronic load
Load sudden change cycle: 1 Hz duty = 50%
 
<Problems>
At the timing when the load has changed from 100% to 0%, the auxiliary power supply (Vcc) voltage by the LLC auxiliary winding of the evaluation board lowers and the IC operation instantaneously stops.
After the operation is stopped, it restarts with the start circuit, but the 12 V output drops by several volts during this period. In case
This failure phenomenon occurs at a considerable frequency.
In case
<Countermeasure and consideration>
① If 47 μF is added to the capacity of the smoothing capacitor C 16 = 120 μF of Vcc,
The drop in Vcc was alleviated and some effect was recognized,
Although the effect is not 100%, the drop frequency of 12 V output decreases.
 
② However, if this capacity 47 μF is added to the current circuit,
The charging time of the start circuit becomes long, and it is not practical because the starting time from input power on to output rising is over.
 
③ As the output current range that maintains the output stability at present, the lower limit of the spec that can be compromised in sudden load change is around 0.3 A (3%), and it seems that it is necessary to add this dummy resistance.
This will be designed to reverse from energy saving and high efficiency targets.
 
④ Consider setting the burst mode level for the above improvement.
Based on the calculation formula of UCC 256304 Japanese version data sheet 8.2.2.21,
To optimize the programming resistance and investigate whether the problem can be improved,
Perform the following.
   When the voltage (upper limit: 1.86 V lower limit 1.14 V) measured by inserting the resistance 10 KΩ into the emitter of the photocoupler (U 2) was substituted into the calculation formula (75) of the data sheet,
When calculated using IFb = 81 μA of the IC electrical characteristics table,
The VLL value becomes a minus value, and the calculated numerical value has no validity, why?
 
⑤ From the contents of ① to ④ above, good improvement measures can not be seen at present,
Is there a breakthrough plan?

Hi Doi-san,

If VCC is dropping to 11.5V during load transient condition you can consider adjusting the turns ratio to operate at a higher VCC voltage on the bias winding. This should help avoid VCC dropout and also may render the extra VCC capacitor unnecessary. You can also adjust the burst mode threshold to make sure there are frequent enough burst packets to ensure the VCC capacitance is getting replenished frequently enough.

I would suggest checking of the opto-coupler is saturating during no load condition and this is causing a delay in the response to the load step. You can try connecting a zener between R20 and R23 to clamp the fast lane current to prevent opto-coupler saturation. This should improve the no load to full load transient.

Please remove R21 when you do the measurement for burst mode. R21 and D10 are sourcing current into the FB node (this circuit is supposed to help avoid opto-coupler saturation). The calculator assumes the opto-coupler current is pulled out of the FB pin and there are no external sources of current to the opto-coupler on the primary side.

Best Regards,
Ben Lough

Hi Doi-san,

Did you get a chance to retest?

Best Regards,
Ben Lough

Hi Ben-san,

1. In equation (67) in the UCC56301data sheet (Japanese), the share of the internal power supply share factor (Kvcrrmp) is
The left term of the calculation formula is converted to the right term so that it is in the range of 0.1 to 0.6, and C1, Cr, Iin, Icomp
The result can be calculated by substitution.
However, in this right term, C2 on the lower side of the voltage divider capacitor is omitted,
It seems as if it does not affect the setting of Kvcrrmp, but C1 = 150 pF, C2 = 0.015 μF
What is the reason for setting range of set C2 value?

2. As a countermeasure proposal for the problem that the output voltage drops in the previous answer mail.
I instructed a plan to change C10 from 0.015 μF to 6.8 nF, but the implementation result was not improved.
In our experiment, we changed the setting of C10 from 0.015 μF to 0.022 μF under the condition of R 14 = 1 MΩ,
Load change 0% (with 1 kΩ dummy resistance between 12 V output terminals) ⇔ 100% variation,
The burst operation at no-load is stable, and there is no drop below UVLO at Vcc,
There was no reduction in output, and there was improvement effect.
Is this setting reasonable? (Other evaluation board constants are default state.)

3. From the results of the above two items, it is said that the capacity setting of the evaluation board C2 = 0.015 μF is not the optimum value in item 1
Think about it, how can I check the optimal set values ​​of C1, C2 capacity on evaluation?

4. With use premised on load sudden change 0 ⇔ 100%, concerning the setting of C1 and C2 capacity values ​​in 1 above,
Please teach the proper range, or the way of thinking.

5. No explanation about Icomp in the datasheet.Is it same as Iramp in the table?