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Original question:

UCC28070A: Questions about the UCC28070A

UCC28070A: Synthesized Questions of UCC28070A

Jankel
Intellectual 731 points
Part Number: UCC28070A

Hi,

Why does the synthesized downslope become zero while V_VSENSE < V_VINAC?

  • 0
    TI__Mastermind 34465 points
    Hello Jankel,
    In this situation where the output voltage is zero or very low and the voltage during the MOSFET off time is not large enough to drive a significant change in the inductor current.
    The equation is V= L*dI/dT
    This means that the downslope (dI/dT ) is zero.

    Regards
    John
  • 0 in reply to John Griffin1
    Intellectual 731 points

    Hi John,

    But it says V_VSENSE < V_VINAC rather than Vout very low.

    For example, Vout=200V, Vin_ac(t=pi/2)=380V indicates V_VSENSE < V_VINAC, but in this situation, inductor current would change a lot.

  • 0 in reply to Jankel
    TI__Mastermind 34465 points
    Hello Jankel,
    Disabling of the downslope only occurs in the situation of power up or recovery from AC dropout. The condition that you describe with a 200V output, 380V input will result in normal operation and there will be a measurable slope in the inductor current.

    Regards
    John
  • 0 in reply to John Griffin1
    Intellectual 731 points

    Hi John,

    1.

    200V output, 380V input is the recovery from AC dropout. It's not a normal operation.

    An actual example maybe this: When your smps is working normally, outputing 400Vdc, but AC dropout happened, after 2 seconds, the ac input recovers, the phase of the ac input now is 90 deg, so, the magnitude of the ac input now equals 265V*sqrt2 = 380V, the output voltage now is 200V because of the 2 seconds discharging.

    So, "200V output, 380V input" is the recovery from ac dropout.

    2.

    What's the specific meaning of the downslope becoming 0? It exactly euqals 0 or just only nearly reaches 0 but a little bit larger than 0?

  • 0 in reply to Jankel
    TI__Mastermind 34465 points
    Hello Jankel,
    The inductor current during the FET off time is synthesized by discharging an internal capacitor during the FET off time. For normal operation the slope of this signal has a positive value. The downslope becoming " zero" means is that it flattens out and that the ic does not detect a change in slope because the internal capacitor does not discharge. In this situation the average voltage on the synthesized current is greater than the IMO signal. This causes the duty cycle to go to zero.
    And that really all that happens here.
    Regards
    John