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TPS1H100-Q1: Pull-up resistor for Vcs, H

Shunsuke Nagata
Genius 13070 points
Part Number: TPS1H100-Q1

Hi, team,

Could you please let me know the range of resistor for Vcs, H? 

Regards,
Nagata.

  • 0
    TI__Mastermind 28260 points

    Hello,

    The CS pin can source up to 30mA. This current causes a max power losses in the device of Vcs,H(max) x Ics(max) = 4.9V x 30mA = 147mW. This causes a junction temperature rise of 41C/W x 0.147W = 6 degree C. Selection of pull down resistor on CS pin can be determined according to power losses allowed by the system. The CS pin is capable of sourcing a minimum of 10mA. For not causing additional junction temperature rise, I would suggest to not pull more than 10mA from CS pin when Vcs is high at upper limit of 4.9V.

    Regards

  • 0 in reply to Mahmoud Harmouch
    TI__Genius 13070 points

    Hi, Mahmoud,

    Thank you very much for your support.

    I would like to know the interval time between over current condition and it's recover while over current condition at Vout.

    Once over current condtion (short condition) is happened at Vout, the Voltage of CS pin becomes the Vcs, H.
    That meaing is
     1. Over current condtion (Short condition) at Vout -> 2. Incrased Iout and cross the thresold, then Stop Vout output (CS pin = Vcs,H) -> 3. After Stop Vout output, decrease Iout and cross the recover thresould  -> 4, Output Vout voltage ( CS Pin = 0V ) -> 2. Incrased Iout and cross the threshold, then Stop Vout output (CS pin = Vcs,H) -> 3. -> 4. -> …

    In above sequence, Could you please let me know the min time between 2(CS pin = Vcs, H) <-> 4(CS pin =0)?
    I guess it should be overcurrent detection time and recover detection time...

    Regards,
    Nagata.

  • 0 in reply to Shunsuke Nagata
    TI__Mastermind 28260 points

    Hello Nagata-san,

    I beleive you are asking about delay times in case of overcurrent or short conditions. Please check attached file for explanation and measurements. Setup conditions is in the second slide. I hope it covers your question and please let me know for further support.

    RegardsTPSxHxxCurrent limit behavior.pptx

  • 0 in reply to Mahmoud Harmouch
    TI__Genius 13070 points
    Hi, Mahmoud -san,

    Thank you for your supports. I would like to know not only delay time for detection of short circuit conditon but recover time.
    I would like to check below condtion:
    Set Short circit condition at Iout.
    1. Stop Iout current -> 2. Release over current condtion and Vout start to rise -> 1. Stop Iout current because short circuit condition still be kept -> 2. Release over current condtion and Vout start to rise->　・・・

    When short circuit is kept, CS pin continue among above procedure #1 and #2 codition. I guess your document explains #1 condition only. Could you please let me know the time among #1 and 2?

    Btw, could you please let me know the meaning of each channel(ch1~4) in your documents?

    Regards,
    Nagata.
  • 0 in reply to Shunsuke Nagata
    TI__Mastermind 28260 points
    Hello Ngata-san,
    I believe the CS response to laod current in #1 and #2 conditions is immediate and max delay is less than 10us. I will verify it on bench test and post the data.
    The meaning of each scope channel in my document is in slide # 2
    Regards
  • 0 in reply to Mahmoud Harmouch
    Prodigy 170 points

    TPS1H100B_waveform.xlsxHello Mahmoud -san,

    I will send you additional information.

    Please check attached File(Customer's waveform).

    Best Regards,

    Hideyuki Muraoka

  • 0 in reply to Mahmoud Harmouch
    Prodigy 170 points

    Hello Mahmoud-san, 

    I will send you additional information.

    Please check attached file(Customer's Waveform)

    Best Regards,

    Hideyuki Muraoka4331.TPS1H100B_waveform.xlsx

  • 0 in reply to Hideyuki
    TI__Mastermind 28260 points

    Hello Hideyuki-san,

    The CS signal responds to load current and the response time is less than 10uS for load step (settling time). The CS signal delay time responding to FET gate pull down is 180us max and it can be seen with the PLZ164W load. This type of load seems to pull current below the current limit (small current pulse between 2 big pulses). When small pulse occurs the CS goes low low after 180us and stays low for 10us (settling time). The CS pulse frequency is the same as the load current waveform. We cannot define CS pulse width. CS supposed to be high Vcs,H all the time in overload condition if the load current is uniform such as resistive load. If the load current is not uniform, CS can have glitch with duration of settling time. This glitches can be filtered by adding RC filter between the CS pin and the MCU.

    Regards

  • 0 in reply to Mahmoud Harmouch
    TI__Genius 13070 points

    Hi, Mahmoud -san,

    Thank you for your supports.

    Is it possble to set the minimum of Tcs, off2?

    Regards,
    Nagata.

  • 0 in reply to Shunsuke Nagata
    TI__Mastermind 28260 points

    Hello Nagata-san,

    The worst case for settling time is the upper limit and this what is important to know. Is there any reason you are asking about the minimum settling time?

    Regards

  • 0 in reply to Mahmoud Harmouch
    TI__Genius 13070 points

    Hi, Mahmoud -san,

    I will ignore the short circuit if it is instantaneous duration. So, I would like to estimate the min time and set it to system to ignore the instance short circuit.

    Regards,

    Nagata.

  • 0 in reply to Shunsuke Nagata
    TI__Mastermind 28260 points
    Nagata-san,
    The response time Vcs to load step is less than 10uS if the load step is below the current limit. The limits of the setteling time is between 0uS and 10uS. If the load step is above the current limit, the Vcs can take up to 250uS to reach Vcs,H. The limits in this case are 50uS to 250uS.
    I hope this answers your question.
    Regards
  • 0 in reply to Mahmoud Harmouch
    TI__Genius 13070 points

    Hi,

    Is the min on time for VCS the 50us?

    Regards,

    Nagata.

  • 0 in reply to Shunsuke Nagata
    TI__Mastermind 28260 points

    Hello,

    Yes this is the minimum time Vcs it takes to switch to Vsc,H in response to over current.

    Regards