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LM46002: BIAS

Part Number: LM46002

Hello,

 

I have got a query about LM46002.

The question is about an issue we are seeing in a LM46002 we use as -15V Buck regulator very similar to the figure 1. in -www.tij.co.jp/.../snva722b.pdf)

We are generating +/-15V with a two converters based on the buck above LM46002 (please note that the above picture depicts the -15V; +15 is very similar arrangement but with the appropiated inverted arrangement.) These two bucks drive a floating load which is a network controller. In some instances we have seen the controller to lock up during power up and down.

Apparently it is been observed that in some instances the bias pin in the -15V buck is back-powered slightly over the -0.3V max voltage limit for this pin as per tds. This causes the output of the -15V to lock-up getting stuck low to a voltage 0.45 V approx and does not seem to recover despite the input voltage is available.

The datasheet does not tell a lot about this bias pin which is connected to a LDO,  and literature available is also quite limited. Coud you please explain the princpiples of operation of the bias pin, the eed for the LDO and what is the actual effect of slight offsets in votlage induced by the loads at this pin- and, potentially ways of preventing it.

Any help would be appreciated.

  • Hello,

    Would you be able to send the schematic for this design? The Bias pin is the source of the internal power supply. You do not want to pull this voltage below the absolute maximum for this pin.

    Best Regards,
    Katelyn Wiggenhorn
  • Hi Katelyn, I can seem to post pictures in here, but the  arrangement we have is identical to the schematic in www.tij.co.jp/.../snva722b.pdf

     

    The load is a A629 network controller powered with +/-15VDC and 5V including  these voltages are generated with another Buck as I mentioned in the previous email.

    We just wanted to check with you to know if you have a history of issues with Bias pin latching off the output of the converter?

     

    Please do verify.

     

    regards

    Linda

  • Hello ,

    Just further to my earlier query;  we have  a few more questions.

     I would like to double check with you on a few other bits awe are not sure about this IC:


    1.We are thinking about pulling this bias pin to a +5V (as per also indicated in the datasheet) with a resistor in series to ensure bias voltage will not be reversed. However we are unsure of the bias current in steady state. Datasheet 27uA during switching operation which is lower that during no switching state. Could you confirm that please?

     

    2. This 5V comes a bit earlier than the input to the Bucks, would it that be an issue/ stress the pin or drive the converted into any invalid configuration? Datasheet does not say anything about it.

     

    Will really value urgent support.

     

    Regards

    linda

  • Hi Linda,

    In regards to your previous question, there is not a known issue with the Bias latching of the output of the converter. The Bias pin can be used as described in datasheet.

    For your second two questions:

    1. I will need to double check on this paramater. I will provide feedback by tomorrow.

    2. This is okay. The internal LDO will be capable of turning on, but it will remain in shutdown mode until the EN voltage crosses the EN threshold.

    Best Regards,
    Katelyn Wiggenhorn
  • Hi Linda,

    I looked at this question and datasheet again.

    The Ibias-nonsw refers to the quiescent current into the Bias pin. This will be the current draw from your 5Vout supply.

    The Iq-switching is the quiescent current when measuring from VIN.

    Please let me know if this is still unclear or if you have any additional questions.

    Best Regards,
    Katelyn