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I'm sorry but please let me ask you more question. As long as I read the figure 21, there are delay time(about 200us) by starting soft start after high EN. Are there the specific value about this delay time?
the 0.9ms is the timing of the internal reference circuit. this is not tested in an application environnement. This includes the delay time ( about 200us) and the ramup until 95% of Vou is reached.
The softstart time tss is check within one of the implemented test-modes in production. During this test-mode the Cout values does not play a role, because the internal ramp of the voltage reference is independent of any external parameters.
For the typical softstart time of tss = 0.9ms the recommended output voltage range - as in the datasheet mentioned - is covered as long as the output load does not drive the TLV62568/9 in overload condition above the specified max load condition.
Could you please tell me why is this parameter critical? how is it affecting the application
Thank you for the reply.
My customer have a possibility using Cout beyond recommended value.
So they worry about whether tss will change depending on Cout value.
Usually we recommend not to go above the recommended output capacitance for the control toplogy of this device. What Cout customer wants to use? is it to power an FPGA?
Could you precise the operating conditions ? Vin, Vout Iout (including load profile)
