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Original question:

LM5035:Unbalanced pvm

LM5035: LM5035:Unbalanced pwm

Andrey Kitov
Prodigy 80 points
Part Number: LM5035

Orange - RAMP

yellow - HO

blue -  LO

COMP=360 uA

CS=0 (closed pin IC )

COMP=460 uA

COMP=560 uA

in all examples, the transformer windings are loaded on resistors without rectifiers and capacitors

when the feedback signal changes (from 560 to 360 μA back), PWM does not restore symmetry to some value of the feedback signal (hysteresis)

  • 0
    TI__Genius 13660 points
    Hi Andrey,

    Thank you for your question, I have asked one of my colleagues to answer this question.

    Regards,
    Teng
  • 0
    TI__Intellectual 1390 points
    Hi Kitov,
    Since there is an internal current mirror on comp pin, small voltage change on comp pin may cause large voltage change on the negative node of PWM comparator and thus make duty cycle unbalance. I do not know how you injected current to comp pin but it is very likely that the noise from current injection caused the duty cycle unbalance issue.
    Regards
    Frank
  • 0 in reply to Frank TANG
    Prodigy 80 points

    Hi Frank,

    1) the current at the COMP input is set by the YOKOGAWA CA 71 current source

    2) even if it is noise, why does it affect the upper channel steadily? At the same time, the lower channel is controlled predictably. PWM The unit in the chip is common, and the behavior should be symmetrical for both channels. The noise really is and it manifests itself in the form of jitter on both channels.

  • 0 in reply to Andrey Kitov
    TI__Intellectual 1390 points
    Hi Kitov,
    I have calculated the expected RAMP voltage at the falling edge of PWM with the injected current you provided for each case. When the current injected to comp pin are 360uA and 460uA, they are equal to 2.2V and 1.7v seperately which are roughly consistent with your provided waveform. When the injected current is 560uA, the calculated RAMP votlage at the falling edge of PWM is 1.2V. It is still equal to the captured votlage at the falling edge of low side MOS, but is inconsistent with that at the falling edge of high side MOS. So I suspect there is noise coupled onto either RAMP voltage or the current souce injected into COMP pin when high side MOS is turned on. Since you did not provide the current source waveform, which may be difficulted to be measured, I can only look into the detail of RAMP votlage waveform and found that there is obvious noise coupled on it. Even though the magnititude of the noise are still below 1.2V and cannot make PWM comparator toggle, it is a clear indicator that there is a noise happened at that moment and very likely coupled onto the current source into comp. If you look into the RAMP votlage when low side MOS turns on, there is no such kind of noise. Therefore, it explains the steady unsymmetrical waveform.
  • 0 in reply to Frank TANG
    Prodigy 80 points

    Hi Frank,

    Indeed the source of the problem was noise. Two oscilloscope probes were connected to the product. The probe that was connected to the CW had poor contact with the ground. Thus, when the upper transistor was turned on, the high frequency current did not return to the desired point, but passed unpredictably on the board through other connections and distorted the feedback behavior.

    Thanks for the support!

  • 0 in reply to Andrey Kitov
    Prodigy 130 points
    From personal experience:
    The source of the peak transient of the high-side mosfet, when open low-side mosfet (through current) is the additional inductance of the tracks of the printed circuit board, as well as the use of mosfet with high recovery time of the reverse parasitic diode. I apply ultra-fast Mosfet or IGBT in over-power disigne (over 3 kW).