UCC27714: N channel Miller boost

Hello BP101,

From many of the behavior descriptions in previous posts and comparisons to other drivers with much lower driving capability, your particular application with the considerations of dynamic behavior of the power MOSFET's and layout may be better suited with the lower driving current.

In many cases, changing the gate drive resistance to lower the drive current and resulting reduction in switching speed achieves the desired results. Not knowing the details of other devices tested I cannot spell out in detail of the differences in the resulting equivalent drive circuit but there are other considerations. There is the consideration of the equivalent resistance of the gate drive network as well as the current capability. If for example, you have a driver with relatively low internal driver device resistance, but is only capable of low drive current, and substitute a high drive current driver with external gate resistance to achieve the same current, you may end up with a gate drive total network resistance that is higher. This may result in larger induced voltage from dV/dt miller charge at the MOSFET gate which is imposed across the higher gate resistance. Regarding dV/dt of the driver output, some devices driver output slew rates are higher than others when not driving to the output current limitation of the driver. It may well be that the other devices being compared have modest drive slew rate capability compared to the UCC27714. Higher slew rates will result in higher peak voltages in the gate drive current loop parasitics.

The UCC27714 driver last year shipped over 1M devices and is used in a variety of power conversion and motor drive applications, so the performance in many cases meets the customer needs.

TI does have a lower current 600V half bridge driver which is the UCC27710, which may be more suited to your application.

Regards,

Richard Herring

Richard Herring said:

The UCC27714 driver last year shipped over 1M devices and is used in a variety of power conversion and motor drive applications, so the performance in many cases meets the customer needs

I would wager a large portion are still sitting on warehouse shelves have never seen the light of day.

Richard Herring said:

This may result in larger induced voltage from dV/dt miller charge at the MOSFET gate which is imposed across the higher gate resistance

I think your missing the point gate drive current is relative to total QG nC of the particular MOSFET and more drive current is required when parallel devices are driven. In our case the single MOSFET is being overdriven at all times of PWM operation no matter what gate drive resistors are chosen relative to total QG. In fact the UCC quickly destroys HO-HS junction when driving even 2.5 amps of gate resistance, (non shorted <10us PW). The gate QG should not short the HO-HS junction as it sink/sources far less then 2.5 amps in either direction, yet it does. How can datasheet claim IGPK +/-4 amps when the HO-HS shorts out at PWM <10Mhz with 25us pulses, non short condition? Again 40 kHz PWM trapezoidal wave form immediately shorted HO-HS with 130 ohms turn on, 51 ohms gate turn off. How can that be occurring from a 4amp gate driver? 

Obviously faster rise times is not better when it comes to MOSFET gate switching as it causes excessive dv/dt even in Infineon's OPTIMOS-FD with 40% improved Qrr over typical industry NFETS, run 10*C cooler. 

Richard Herring said:

TI does have a lower current 600V half bridge driver which is the UCC27710, which may be more suited to your application

We need the safety current margin for parallel MOSFETS but can't get acceptable results from lower QG settings. The competitions gate driver 600V drive, 350mA source, 650mA sink (<10µs PW shorted) with 120 ohm gate turn on and 60 ohm gate turn off never shorted HO-HS on a single driver. Nor does Qrr (dv/dt) impact the LO side MOSFET drain >-10v or HO side source transient as does with the UCC. The UCC should dynamically adjust bias drive on the HO side internal Totem pole relative to sink/source demands, yet it does not. The HO/LO boost NCHAN over drives up to Miller plateau racing into Qrr band gap, even with very fast Trr there simply is not enough time for fully snubbing back EMF (AKA synchronous rectification). That would be errata in our view and should be corrected in a later version UCC design. TI bench test may too reveal Qrr race condition occurs in UCC with power MOSFETS driven by over lapping signal pairs HI/LI inputs. That is not complementary PWM signal pairs as they overlap each other with dead band times added in.

Several times have ask for TI supervisor to test TIDA-00778 with overlapping PWM code. It may very well be overlapping signals cause UCC27714 to have undisclosed errata with  power MOSFETS. 

Hi Richard,

Richard Herring said:

Regarding dV/dt of the driver output, some devices driver output slew rates are higher than others when not driving to the output current limitation of the driver.

Seemingly the complaint includes odd stressing HO-HS junction from less than rated drive current (4Amps) being applied to power MOSFET. After further review of each driver, both were noted producing LO side dv/dt with large BLDC motor. So the UCC LO side dv/dt (-10v) is not quite as bad with competitions (-8v), yet still present.

The competitions driver has about as much HO ringing as UCC driver with larger BLDC motor. Perhaps the high side HO faster speed coupled with faster MOSFET rise times somehow sources to much current via HS. Competitions driver had 9.2 series R into VS(HS) & Schottky diode to COM from VS pin. UCC has little to no current regulation Vmotor (HS pin) and HB pin 3.3 ohm VDD however the SINK current path occurs HO to HS, not HB.  

Perhaps why the competitions driver VS-HO is safe guarded (9.2R) from Vmotor current surges?  The VS pin to Vmotor (9.2R) was our choice added to stop HO latch up per vendors technical bulletin. Might we expect a Wiki update to explain why HS-HO is being so easily stressed?            

Hello BP101,
It sounds like the previous design you mention with the competitors driver has a 9.2 ohm resistor from the power train switch node to the driver IC HS pin, can you confirm?
If this is a difference in the board design from the UCC27714 and the competitor driver, this will result in differences in the drive output circuit and limiting stress on the driver HS pin. The 9.2 ohms will be additional gate resistance in the gate drive current loop on the high side driver for turn on and turn off. Also voltage transients present on the power train switch node will have a limited current path to the IC HS pin.
Have you tested the UCC27714 with the same 9.2 ohms on the HS pin to the switch node to have the equivalent circuit you describe with the other driver?

Regards,
Richard Herring

Hi Richard,

Richard Herring said:

Have you tested the UCC27714 with the same 9.2 ohms on the HS pin to the switch node to have the equivalent circuit you describe with the other driver?

Sort of the point requesting any confirmation since datasheet suggest HS pin has excellent dv/dt rejection. The point of competitions AN6076 suggests parasitic SCR latch up of HO missing pulses HI as Cboot over charges when or if VBS approaches COM. Note 80vdc HB is no where close to 600v HB. Listed conditions of AN6076 was for older drivers that newer UCC driver rejects dv/dt down to -18v @400ns. It seems HS-HO may be stressed by rapid 25µs HV pulses entering HS pin, again LO dv/dt is less (-6v) with Schottky/9R added to competitions VS pin. None of AN6076 fixes should be required for UCC27714 as figure 53 graph shows -80v to -18v being more robust than -9v of much older competitions driver. Seemingly the idea was not only to make UCC have best in class propagation delay (90ns) but to stop dv/dt latch up of HI and or Cboot over charging via UVLO, right?  

The UCC datasheet has not made clear what COM being tied to low side NFET source overcomes other than theory a minimal 2mohm shunt voltage drop. Does COM path derived from low side NFET source stop HS-HO stressing? Why is HO-HS immediately stressing from 40kHz mostly center UCC during overlapping PWM HI/LI drive only when HB=80v but not HB=24V? Again HO-HS does not stress from 12.5kHz PWM when HB=80vdc. That is why TI engineering needs to confirm if a timing issue in Miller speed leads to higher than expected transients when or if NFET Qrr is being over run at faster 25us HS pulses thus clipping Trr cycles short in the process. Other words synchronous rectification is being cut short and inductive high voltage transient develops striking HS instead of producing useful motor power. That does not describe HS dv/dt rather it describes some kind of HS pin errata, UCC should not be immune to HS parasitic SCR latch up by the newer updated design, right?  

   

BTW: Competition has driver with same pin out FAD7191. Though HI/LI to HO/LO propagation & MT are bit slower it would be interesting to see how UCC stacks up to it with no added updates. Note competition lists AN6076 even with newer FAD and seems a bit dimwitted since they are aware older drivers exhibit SCR latch up. Our opinion is TI engineering should be first to test TIDA-00778 with FAD driver and note any differences via community Wiki.

Hello Richard,

Richard Herring said:

It sounds like the previous design you mention with the competitors driver has a 9.2 ohm resistor from the power train switch node to the driver IC HS pin, can you confirm?

Adding RVS 9.2R was optional to replace Rgate. Competition driver with RVS=9.2R, Rboot=1R, total Rgate=129.2R and UCC Rgate=130R. The other part of AN6076 reducing Rboot from 10 ohms to 1 ohm, with RVS=9.2R  Rboot=10 ohms and NO 10uf bias caps existed on VDD. Hence the need UCC sanctions further TI bench testing thusly becomes prudent. Further testing is warranted since we have 6 or more stressed or corrupted parasitic HS-HO diodes. Same motor with our original inverter competitions gate driver versus UCC27714 configured as datasheet suggests.

Have to question VDD source may be an issue with 485mv AC ripple (TP+15V) during motor run, +24v buck down +15v output with two 22uf parallel ceramic caps and one 22uf electrolytic near center UCC 19.02mil wide traces to each 5.1R VDD bias. That 485mV ripple (X1 probe) seems a bit high and not sure of ripple each VDD pin 7, should expect less ripple at each VDD pin 7 with 10uf ceramic cap, right?

Yesterday placed Schottky diode across HS pins to COM each UCC and phase pulse peaks still reached 140v on 3rd phase. Was hopping Schottky alone might help to reduce the frequency of transients, perhaps a little difference was noticed.  

Richard Herring said:

With 15V VDD ~480mV peak tp peak noise should not be an issue with the driver operation

I took out the 1uf caps COM-VDD, might explain higher peaks forming >450mV AC like wave from at +15v supply. Later probing near UCC +15v bus roughly 48mV ripple, not counting the PWM pulse spikes. Adding 2200pf caps on HO-HS & LO-COM did not seem to help, rather causes more inverter output pulses spiking below COM and on LO peak 18V a bit more often. Oddly LO never seems to be stressed, only HO-HS was being stressed with or without 1uf COM-VDD filters.

Richard Herring said:

Placement of the VDD capacitor close to the VDD and COM pins is important to minimize additional peak to peak noise from the pulsed current flowing in the board trace inductance

My thought was to parallel 100n versus 1000n COM-VDD at UCC pin 5-7 0805 pads. The 10uf is tied SGND has far less noise than COM/AGND, both are only 20mohm ferrite apart at MCU and DC inverter. The odd thing is scope channel/s set 5v vertical the HO dV/dt  > -18v but is -0v on 10v vertical scale. The negative pulses seems like vertical aliasing, not HO dV/dt but who knows it might be -18v dV/dt?    

Hi Richard,

One thing to note competitions FAD7191 driver allows higher values of dead band >100ns without producing 100ns +5v peak phantom pulse on LO. Besides COM pin layout not being discussed in datasheet, there is not much difference if any noticed either way it connects to ground or NFET source on either driver.   

An accident with MCU control of PWM recently occurred UCC center phase, shoot through destroyed UCC, two NFETS odd attack center driver again. Notably competition driver allows even 320ns dead band with no phantom pulses LO being produced. Seemingly MT or other timing issue HI/LI leads to phantom pulses unless dead band was set <100ns. Needless to say was reluctant to set dead band <100ns but figured TI experts had fully tested UCC timing per datasheet specifications. Sadly UCC does not seem well suited for PWM frequencies <20Khz with overlapping PWM signals HI/LI without timing issues.