UCC28950: Question about Hiccup mode off time

Hello Satoshi-san

You are correct, the 'Hiccup mode off time' is the time from when the MOSFETs stop switching as the SS/EN pin passes through the Pull up threshold (3.6V) and reaching the 'Output Enable Threshold' of 0.55V.

There are a number or reasons why the time might be different to the value calculated from eq 20 and 21

1: There is a wide tolerance on the IHCC current, 1.9uA to 3.2uA. High currents will reduce the time.

The discharge curve is not linear - this means that the current discharging the SS/EN capacitor is not linear or the capacitance is not linear.

2/ Sometimes a 825k resistor is used at the SS/EN pin - this will sink additional current from the SS/EN capacitor and reduce the time

3/ The user may have added some external switch (a small MOSFET for example) at the SS/EN pin - this too can sink some additional current and reduce the hiccup time. It will also give you a non-linear discharge curve (exponential)

4/ Low voltage ceramic capacitors can have a significant voltage coefficient of capacitance - this will cause a non-linear discharge curve even if the current is constant.

I'd suspect that some or all of the above effects are causing the difference between expected and measured values.

Please let me know if you need any more details.

Regards
Colin

Colin-san

Thank you for reply,
I think that the reason are 825k resistor and IHCC tolerance.

Customer want to set large percentage of off time.
Is there way to set keep on-time and increase off time?

Best regards,
Satoshi

Hello Satoshi-san

You can increase the off time by adding a resistor from the SS/En pin to VREF. This is a relatively simple approach and I've outlined it in the attached document. If the customer needs better control of the OFF time then their best option would be to use an external enable signal to control a small MOSFET at the SS/EN pin.

Please let me know if you need any more information - .

/cfs-file/__key/communityserver-discussions-components-files/196/SS_5F00_EN-pin.pdf

Regards
Colin

Colin-san

Thank you for good file.

Sorry for additional question,
Customer want to long OFF time for a few second, is this possibility to any risks?

Reason of long OFF time(= long switching cycle) is reduce power dissipation.

Best regards,
Satoshi

Hello Satoshi-san

There should be no problems in having an off time of about 1 or 2 seconds. Using Eq 20 in the UCC28950 DS you can calculate that a 1uF soft start capacitor will give you about 1.25s off time. The tolerance on the IHCC current is 1.9uA to 3.2uA so you can expect a similar variation in the off time.

The soft start capacitor controls both the soft start and off times during hiccup so these times are not independent. The soft start current is 10 times larger than the IHCC current so you will see approx 1:10 ratio in the two times.

The ratio of the IDS to IHCC also sets an approx 1:10 ratio between the time spent in current limit and the off time . The average dissipation in the power stage will depend on this ratio and increasing toff by increasing Css won't affect this ratio.

If the customer wants to modify this ratio to keep short soft start and current limit times but to increase the off time then I think we would need to look at some external circuits. I don't have any details for this but if the customer was interested and had some specific off times in mind then I am sure we could suggest something. If their system included a microcontroller then that would make things easier.

Regards
Colin