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TPS2491: Behavior of PG pin

Shinichi Inoue
Guru 21701 points
Part Number: TPS2491

Dear Specialists,

My customer is considering TPS2491 and has a question.

I would be grateful if you could advise.

---

I confirmed the behavior of the PG pin and have three questions.

Could you please see attached schematic and waveform.

question about PG pin .pptx

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I appreciate your great help in advance.

Best regards,

Shinichi

  • 0
    TI__Guru** 105361 points
    Hi Shinichi,

    I will go through the test waveform and clarify.

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    TI__Guru** 105361 points
    Hi Shinichi,

    During startup, PG output depends on VDS of external FET. The VDS has to fall below 1.25 V and then wait 9ms (typ) to assert PG output HIGH.

    During an fault, the device goes into protection mode and VDS increases. Once VDS increases above 2.7V, the PG output goes LOW after 9ms (typ) deglitch time.
    In case, device is disabled by doing EN < EN_L, the PG output goes LOW after 9ms (typ) deglitch time.

    Refer Section "7.3.9 PG" in the datasheet and let me know if there are any further questions.

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Guru 21701 points

    Hi Rakesh,

    Thank you for your reply.

    I understand PG output depends on VDS of external FET, not EN and Vccc.

    I'll share this information with the customer.

    I appreciate your great help.

    Best regards,

    Shinichi