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UC1525A: UC1525AJ Device Design Question Consultation

Part Number: UC1525A

At this stage, the main reason why we consulted you about this UC1525AJ device is that the IGBT and the voltage regulator on the driver board often burst during the operation of our products. In view of this, we have investigated the application of this device on our current schematic. Is the rationality of the peripheral device design for this device reasonable? I hope to get your assessment, is there any unreasonable device selection? If not, how to improve? I hope to get your guidance and analysis.

 

NOTE:1、How to control the parameters of the two pins of OSC SYNC and OSC OUT? How much control can you guarantee that this UC1525AJ is working properly?

       2、Regarding the UC1525AJ device, how do you think Zhou Wei is the most reasonable? Is there a circuit design that can be recommended for this UC1525AJ device?

 

  • Hey Gong,

    What parameters of SYNC and OSC OUT are you trying to control?

    I am not sure what Zhou Wei is and we dont have a reference design for the UC1525A.

    Thanks,

    Daniel

  • Dear TI Technical Engineer,

         Thank you very much for your attention and answers to our questions, your help in analyzing our questions is very important. In response to some of your questions before, I will explain again here to help you better help us analyze.

    PWMBCY

     

     

    PWMBCX

     

    PWMBCZ

     

    NOTE:Figure 1 is an example of the application of UC1525AJ chip by our company.

    Figure 1

     

    At this stage, the main reason why we consulted you about this UC1525AJ device is that the IGBT and the voltage regulator on the driver board often burst during the operation of our products. In view of this, we have investigated the application of this device on our current schematic. Is the rationality of the peripheral device design for this device reasonable? I hope to get your assessment, is there any unreasonable device selection? If not, how to improve? I hope to get your guidance and analysis.

     

    NOTE:1、How to control the parameters of the two pins of OSC SYNC and OSC OUT? How much control can you guarantee that this UC1525AJ is working properly?

           2、Regarding the UC1525AJ device, how do you think Zhou Wei is the most reasonable? Is there a circuit design that can be recommended for this UC1525AJ device?

    5th foot on the 2st foot test waveform

  • Can you tell us your email easily? I have a clearer question on the side of this issue because of a WORD file, but this does not seem to be able to upload.
  • Hey Gong Fu,

    Is IN- and IN+ the error amplifier inputs? It seems like you are always driving the part at max error.

    These inputs are generally connected to a resistor divider from the output and a voltage reference.

    Thanks,

    Daniel

  • 1. I uploaded the design schematic diagram of the UC1525A device in the attachment. Do you think our design is reasonable? How to improve the unreasonable place? According to DATESHEET of the UC1525A device, how do you see problems with our design?
    2. What is the reasonable error range for driving the device with IN- and IN+? Is there a range that can be recommended for us?
    3. The PWM generated by OUTA and OUTB of UC1525A device, we drive IGBT directly through series of devices through optocoupler. The problem that arises now is that our IGBTs are easily burned.
  • Hey Gong,

    As stated in my previous email, it seems you are forcing max duty cycle by always having the In- at ground and the IN+ at VREF.

    This is possibly why what you are driving is blowing up.

    IN- should be connected to the output voltage through a resistor divider to make it the same as VREF.

    Thanks,

    Daniel

  • Hey Daniel,
    1. How should we design the parameters of each function pin in the UC1525AJ chip during the design improvement process? (For example: What specifications should be placed on the 1st and 2nd feet?)
    2. In your previous answer, “always driving the part at max error”, I don’t understand what it means. According to our current design, what is the error? In your opinion, what is the most reasonable reason for this error control in our design?
    3. According to your opinion, we will divide the IN-series resistors and connect them to Vc to ensure the same as Vref. What exactly does this mean? Finally, what other pins need to be improved in our design? Such as Ct, Rt, etc.
    4. Can you tell us the detailed reasons for the IGBT blow up? What are the parameters of OUTA and OUTB of the specific UC1525AJ chip? Should we control the extent to which this IGBT blown up is avoided?
    5. Regarding the OSC SYNC and OSC OUT pins, what range of parameters do you think we should give to this UC1525AJ to ensure the normal operation of this chip?

    Thanks,

    Gong
  • Hey Gong,

    From your questions I am confused on what you are using our device for.

    Is your design a certain topology?(Example: Buck, Boost, ect.)
    IF so what is the input voltage to the topology and the output voltage?
    Do you have a target switching frequency?
    How much current are you trying to supply?

    Thanks,
    Daniel
  • Hey Daniel,
    Thank you for giving me the patience to answer my series of questions.
    1. What are the problems I have explained that you don't understand?
    2. The full-bridge topology circuit used by our IGBTs under normal working conditions.
    3. The VIN+ and Vc of the UC1525AJ chip are both 15V to GND, and the output is about 28V.
    4. The switching frequency we control is 7.5KHZ
    5, In addition to the improvement method that you mentioned before (increasing the voltage divider resistance to ensure that it is consistent with Vref), at present, we have some unreasonable points in the design schematic diagram of UC1525AJ chip. I hope you can help us point out the unreasonable place. In the face of irrationality, how should we improve?
    Thanks,
    Gong
  • Hey Gong,

    On all the schematics you have provided to me the error amplifier is not connected to the output of the full bridge which will cause issues at the output of the UC1525A.
    The output of the full bridge needs to be fed back to the UC1525A such that the full bridge output can be regulated by the PWM controller.

    The waveforms you have provided look like the spikes are just noise in measurement.
    Are those spikes on the waveform what you are worried about?

    Thanks,
    Daniel
  • 1. Our subsequent improvement scheme is as follows: short the IN-series voltage dividing resistor to Vc, and finally let the IN- terminal be connected to GND, Vref remains unchanged, and Vin+ and Vc are separately connected to the power supply. What do you say is the same as Vref, can you explain which parameters? This can be used as a reference in our company's internal testing process.
    2, UC1525AJ Ct feet, you need to connect a capacitor in your datesheet, we do not increase the capacitance in the design schematic, will this affect? If so, can you tell us how much capacitor should we add?
    3. Are the other pins of our UC1525AJ chip designed reasonably? For example: Is the Rt\DISC\SOFTSTART\COMPN pin design reasonable? If it is unreasonable, I would very much like to get your guidance and you can experiment with it as a reference.
    4. I don't worry about waveform spikes, because this is due to the long drive line when I tested.
    Thanks,
         Gong
  • Hey Gong,

    1. Please connect IN+ to a reference voltage, this determines what reference voltage IN- will try to regulate to.
    2. Please connect IN- to a resistor divider from the output of the full bridge, this helps regulate the output voltage.
    3. Please connect Ct to a capacitor to ground, this determines the frequency of operation.
    4. Please connect Rt through a resistor to ground, this determines the frequency of operation.
    5. Please connect a capacitor through Soft Start to ground, this helps determine soft start.
    6. Please connect type 2 compensation (Using OP Amp) to the COMPN pin based on the following app note:
    www.ti.com/.../slva662.pdf

    This will determine frequency response.


    Thanks,
    Daniel

  • Hey Daniel,

           Since your reply is in the middle of our Spring Festival holiday, the email did not reply to you in time, and I am sorry to say this to you. Thank you for your answers and support to our feedback series, and we wish you a happy new year.I have received your reply, but there are still some questions, so you still need your support. as follows:
    1、According to our current design and application of UC525AJ chip, can you help us identify the design flaws, and what defects will affect us? Such as this affects the logic of UC1525AJ normal work.
    2、What is the specification of the resistors and capacitors used in the improvement of the design and application of the UC1525AJ chip? (eg 10K, 0.1uF, etc.). In addition, if you follow the improvement suggestions, we need to focus on testing the parameters of the UC1525AJ chip after the improvement? What is the value of these parameters to indicate that the design is reasonable? This way we can compare and reference during the test.
    3、According to the series of questions I have consulted from the beginning to the present, you think that I still have those tests that need to be verified one by one, and then I will continue to consult you about the UC1525AJ chip design application series.
    Thanks,
         Gong
  • Hey Gong,

    1. All the design flaws I listed will affect how the part functions and often cause it to not function properly.

    2. Those values are completely dependent on your design and what the full specifications of the design are.

    3. Tests are generally done to satisfy customer design requirements based on the end product. I would follow whatever testing you are required to do for your end product.

    Thanks,

    Daniel

  •   Hey Daniel,

           Thank you very much for your continued technical support.Your last reply, I still have some questions that I can't understand, I hope to get your explanation again.
           For the UC1525AJ chip application design, can you explain the difference between our current design and the improvement scheme you gave? According to the difference, what defects do you think our application design has (can be detailed)? In addition, what are the advantages of the improvements you give us?
           Our products use four IGBTs and are driven by OUTA and OUTB of UC1525AJ. After OUTA and OUTB come out, they are divided into 8 channels and then connected to the driving end of the IGBT. Now the proportion of IGBT blown up in more than 200 products has reached 25%.
           According to the design of our UC1525AJ chip, what do you think is the root cause logic of the IGBT blown up (what way leads to IGBT blow up)? Is the frequency or other parameters causing the blow up? I really hope to get your detailed instructions, thank you!
    Thanks,
     
    Gong
  • Hey Gong,

    I believe the reason for the IGBT blowing up is because the device is not properly being used. The schematics you have given me have shown the device being used in a way the device is not intended to be used.

    The changes I described are changes that will allow the device to be used the proper way. I am unsure why our device even works in the schematics shown to me.

    Thanks,
    Daniel
  • Hey Daniel
         Thank you for your patience.
         According to your statement, we did not use UC1525AJ correctly, causing IGBT to blow up, which may be the most fundamental reason. In view of this, you can elaborate on how we are currently causing IGBT blow up during the design process of UC1525AJ. We have potential defects in the design of the UC1525AJ, and we don't understand the impact logic. Therefore, I hope to continue to get your answer. Thank you!
    Thanks,
     Gong
  • Hey Gong,

    Even with the operation of our device being questionable, the two ways our device could cause the IGBT to blow up is if the gate drive is higher than the max Vbase of the IGBT or the currents get too high and the IGBT gets too hot.

    Thanks,
    Daniel
  • Hey Gong FU,

    From the pictures you have sent, if it is our device, the most likely cause will be the device having an output voltage signal too high for the IGBT. This in turn would cause the IGBT to break down and constantly sink current causing the damage you see here.

    What is the VGE voltage of the IGBT? What are you seeing at the output of our device?

    Thanks,

    Daniel

  • Hey Daniel,
    Thank you for your detailed analysis and answers to our questions.
    1. The VGE of our IGBT is about -9V to 12V.
    2. In order to understand in more detail the defects of our UC1525AJ design application, what information do I need to provide here?
    3. Through the detailed communication between us, can you help me summarize all the defects in the design and application of our Halo UC1525AJ chip?
    4. Regarding the design and use defects of our UC1525AJ chip, according to the improvement plan that you gave us, what test results do I need to provide you here? So that you can continue to assist us in the analysis.
    I hope to hear your detailed answer, thank you!

    Thanks,
    Gong
  • 2. Can you provide a full schematic? We can take this offline if necessary.

    3. I will discuss this if a schematic is sent.

    4. Check to see if the output of the UC1525 is higher than 12 V.

    Thanks,

    Daniel