LM5067: Review of LM5067 Design calculation for 20A and 12A current

Hi Nadim Ahmed,

Welcome to E2E!

I will review the sheets and get back to you.
Can you share your project details.

Best Regards,
Rakesh

Hi Nadim Ahmed,

Can you check with stronger FET something like PSMN4R8-100BSE. Else, we need to add dvdt startup circuit at GATE. In the later case, I prefer and suggest to use new device TPS23521, which offers more flexibility.

Can you have a look at TPS23521 and let me know your opinion

Best Regards,
Rakesh

Hello Mr. Rakesh,

Thank you for the response. Could you please guide us to select R_DS(on) resistance at Tj, _DC temperature. As per design calculation sheet for R_DS(on) = 4.8 mili ohm the required T_j,DC is 110 degree C, while as per datasheet of PSMN4R8-100BSE, the drain source on-resistance R_DS(on) = 4.8 m ohm at T_j,DC=25 degree C. Now, if the value of R_DS(on) @ 110 degree C (from datasheet) is placed in calculator sheet, the T_j,DC   temperature automatically changes, since T_j,DC is dependent on R_DS(on). Please clarify this.

Regards,

Nadim Ahmed

Dear Mr. Rakesh,

The design calculation sheet for 20A and 12A operating current are attached. Kindly review these. Here, below are the few points that need to be clarified.

(a)   As per datasheet the thermal resistance R_θ,JA = 50 K/W with MOSFET minimal footprint. However, the design calculation are done with R_θ,JA = 30 K/W and 40 K/W for 20A and 12A current respectively. Is it possible to have reduced R_θ,JA for MOSFET??

(b)   For 20A operating current, it is difficult for us to set R_{DS, ON} and T_{J, DC} parameters using a single MOSFET even with reduced R_θ,JA=30 K/W. Therefore, the design calculation is shown with 2 MOSFETs in parallel. But, due to space constraint in our PCB, we can not use dual MOSFET config. Is it possible to have the design with single MOSFET for 20A operating current??

Thanks & Regards,                                                                                                                                                                                                                                                                                                                            NADIM AHMED, C-DOT, New Delhi

LM5067_Design_Calculator_20A.xlsxLM5067_Design_Calculator_12A.xlsx

Hi,

Thank you for the clarifications.

The design calculation of LM5067 with low R_on FET like CSD19536KTT and reduced fault timer capacitance fails to meet the SOA margin. Therefore, we are planning now to use TPS23521 for 20A operating current as you suggested earlier.

The design calculation sheet for TPS23521 is attached. Kindly review it and give us your feedback. Kindly also tell us whether we need heatsink for the transistors in this design.

Regards,

Nadim Ahmed

 TPS2352X_Excel_Tool_Baytop-20A.xlsx

Hi Nadim Ahmed,

Even with TPS23521 device, 20A solution with a single FET is not possible because the temperature rise in steady state is determined by the FET Rds_on.

If you leave Q2 blank in the design calculator, it pushes the Tj of Q1 to 177C

The advantage of TPS23521 over LM5067 is at higher currents where multiple FETs are needed. TPS23521 allows single stronger SOA FET for Q1 and multiple "low Ron" FETs for Q2 there by reducing overall solution size and cost. Please refer application note for more details http://www.ti.com/lit/an/slvae07/slvae07.pdf

So for your design, two FETs will be needed irrespective of the controller

Best Regards,

Rakesh

Hello,

The design calculation for both the LM5067 and TPS23521 for 20A current are attached. We have used 2 MOSFETs for both the cases.

For device TPS23521 if we use Q2 transistor along with Q1 the steady state junction temperature reaches 128⁰C, while for LM5067 the steady state junction temp. is 96⁰C. Do we need hitsink for MOSFETs in the TPS23521 H/S circuit, since the design is with R_{θ, JA}=45 K/W which is only 5 K/W less than minimum footprint R_{θ, JA} i.e. 50 K/W.

Kindly review both the designs (i.e. LM5067 and TPS23521) and suggest us which one would be the better solution.

Regards,                                                                                                                                                                                                                                                                                                                                    Nadim1374.TPS2352X_Excel_Tool_Baytop-20A.xlsxLM5067_Design_Calculator_20AF.xlsx

Hi,

The ambient temp is entered differently in the two designs. Is it 75C ? If yes - it will bring down the steady state junction temperature to 118C in TPS23521 design.
I suggest to proceed with TPS23521 solution as it helps to scale up for your future high current designs. You would require, more PCB area as heat sink to lower Rθ, JA. Please use at least 1-inch2 PCB area dedicated for FETs however I feel the generated heat will spread to the adjacent PCB area and help especially if the board size is of decent size.

Best Regards,
Rakesh

Hi,

Do you have any follow up questions?

Best Regards,
Rakesh