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Duty cycle of HFCLK

In TWL5030, the duty cycle requirement is 45%~55%.  Customer is asking if it's possible to use a 40~60% duty cycle clock.

By the way, this duty cycle requirement is based on TWL5030 or OMAP3?  Or both of them?

Thanks,

Antony

  • Antony,

    Duty cycle requirement is based on OMAP alone. As long as you satisfy the spec for OMAP that will be sufficient. The clk circuit on the power management device does not modify the clk duty cycle. It acts as a buffer and slicer(in case a sine wave is used).

     

    Regards,

    Gandhar.