Hi experts,
I'm designing 13s BMS using BQ7694003. I'm having trouble writing to BQ registers. The IC doesn't give an ACK on the 9th cycle. The SDA line isn't pulled LOW during the 9th cycle. The same issue had been brought up earlier https://e2e.ti.com/support/power-management/f/196/t/323329 But neither the solution nor the cause was pointed out. I changed the BMS IC but still the issue wasn't solved.
I have studied the code given at http://www.ti.com/lit/zip/sluc583 and the ap note http://www.ti.com/lit/pdf/slva626 and accordingly have written my code.
In my I2C setup -
Host MCU -> MASTER (always)
BQ76940 -> SLAVE (always)
I believe this setup is right because BQ doesn't generate SCL, hence it cannot be a MASTER in any event (tx or rx). Thus, it'll always be a SLAVE and MCU will be the MASTER always because it generates SCL. Is my understanding correct?
Moving on to I2C software. To explain my software flow, I will consider the example of CC_CFG register
BQ_addr = 0x08 or 0000 1000
CC_CFG : addr = 0x0B or 0000 1011
data = 0x19 or 0001 1001
CRC = 0x89 or 1000 1001
CRC poly: x8 + x2 + x + 1 = 1 0000 0111
CRC is calculated over: BQ_addr(8bit) | CC_CFG(8bit) | DATA(8bit)
0000 1000 | 0000 1011 | 0001 1001
since the power of CRC poly is 8, 8 zeroes are appended to the above binary number and then CRC is calculated
I got 0x89 as the CRC for the above case
The whole I2C frame is then transmitted to the BQ. The BQ sends an ACK after every byte it receives. The frame format is
START | SLAVE_ADDR(7)+W(1) | REGISTER_ADDR(8) | DATA(8) | CRC(8) | STOP
(n) -> indicates the number of bits
SLAVE_ADDR + W = 0001 0000 (BQ_ADDR left shifted by 1)
REGISTER_ADDR = 0000 1011
DATA = 0001 1001
CRC = 1000 1001
SLAVE_ADDR is the BQ address left shifted by 1 bit. 8th bit of this field is zero which indicates MASTER is in transmission mode (MT mode). Thus, the MASTER will write data into the SLAVE's register.
Now the problem is, BQ isn't sending an ACK on the 9th cycle after SLAVE_ADDR + W. SLAVE_ADDR + W byte is transmitted successfully but a NACK is given by the BQ on 9th cycle, SDA isn't pulled LOW.
Below are the voltage readings I observed at different pins of the BQ IC -
(ALL VOLTAGES ARE WRT GROUND)
TS1 = 0.0 V (after bootup)
TS2 = 20.2 V
TS3 = 36.4 V
CAP1 = 3.28 V
CAP2 = 23.7 V
CAP3 = 40.01 V
REGSRC = 18.4 V
VC5X = 20.4 V [C1,C2,C3,C4,C5]
VC10X = 36.7 V [C6,C7.C8.C10]
BAT = 53.2 V [C11,C12,C13,C15]
PACK+ = 53.3 V
I have used 3 10k NTC thermistors, each soldered between TS1-gnd, TS2-VC5X, TS3-VC10X. When I press the BOOT button, the TS1 voltage goes up to 2.7 V. Also, BOOT signal is applied after connecting the battery. I2C communication is started after BQ boots up.
I have also used a 3.3 - 5v bidirectional logic level shifter to enable safe and correct communication between the 5V MCU and 3.3v BQ IC.
So, what can be cause of the mentoned issue? Why is BQ not sending an ACK? (PS: I dont have access to an EVM board, so dont ask to test the I2C on an EVM)