Original question:
Hi Bing-san,
My customer is using Fuji-elec. LLC IC.
The IC is unstable during power on stage.
They want to stop driving pulse of UCC24624 until LLC stage stable.
By increasing the value of capacitor terminal REG or VDD, driving pulse can be delayed.
Which is better? And teach me the upper limit of both capacitance.
Doi-san,
I am not quite sure what you mean the LLC operation not stable. UCC24624 can handle different operation conditions of LLC, it might behave differently than the ST part and avoid the issue.
Regardless, if we want to avoid the SR operation during the start up, there are several way to delay the turn on of SR controller.
1. You can always use the simple way that you have in your description. The RC time constant on the VDD filter will delay the turn on. There are several things to watch out
a. The voltage drop on the external resistor. Please help to calculate the voltage drop on the resistor to make sure it still can provide enough voltage on VDD pin when the SR is fully operation
b. Fast turn off and back turn on. Because of the large time constant, when the converter shuts down and turned back on in a short time, there might still be enough energy stored in the VDD cap and LLC SR controller is not fully shut down yet. If the LLC is still operating strangely, you might see the same issue. You can always parallel a diode with the resistor (cathode connected to the output and anode connected with the VDD) so that the VDD cap can be discharged when the output is discharged.
2. Using external controlled switch. You can have a switch to disconnect VDD until the LLC output voltage is high enough. A simple comparator followed by a MOSFET should be able to do the job. The comparator decision can be made based on the LLC output voltage or even adding an extra delay. A simplified circuit can is shown here.
3. Another way you can do it is to short REG pin to ground. The linear regulator from VDD pin to REG pin has a current limit protection so that you can safely short REG pin to ground without worry about damage the IC. You can simply use a depletion mode FET with the REG and control its gate through a voltage divider from the output. This way, during the startup, the depletion mode FET is on and REG pin is shorted to ground. When the output voltage increases, the depletion mode FET gate voltage rises. Depending on the divider ratio, the depletion mode FET can be turned off by a preset output voltage.
Let me know if these are clear. Basically, the UCC24624 can be disabled through the VDD pin or REG pin. If you can control these two pin voltages, you should be able to delay the turn on.
Thanks.
Bing
