LMG1205: HS Pulse Collapse When external FET is Loaded

Hi Matt,

thanks for reaching out on LMG1205, Im the apps engineer for this device.
I understand that when your HI input attempts to turn on HO, the output wont reach all the way up to 5V. This happens at pretty low frequency. Since the frequency is low there should be plenty of time to replenish the bootstrap but maybe too much on time to keep the high-side at 5V due to leakage or too small bootcap value.

When I calculate your boot capacitor value for your system (using EPC2108 which has very small gate charge of about 300pC plus about 1nC of HB quiescent current and 2nC of reverse recovery charge on rising edge) I notice that about a 400nF cap is needed for 0.01V variation in the boot voltage during turn on. Its possible the additional parasitic switch node capacitance from layout is requiring extra the bootstrap cap of 650nF to charge the high-side the entire on time with out reaching UVLO.

a) what is your VDD cap value? The VDD cap replenishes the bootstrap during off time and could prevent the bootstrap from charging up completely if too small (section 8.2.2.1 of the datasheet helps with this value)
b) can I review your schematic to see why anything less than 650nC might not work?
c) does the issue get better at high-frequency? typically bootstrap circuits tend to get tricky at longer on times since the leakage from gate to source (removed from the bootstrap) can hinder the high-side.
d) can you confirm HB-HS voltage is not reaching UVLO (3.4V)? if UVLO is being reached after some time after turning on its likely leakage is the issue.

to answer your questions:
1) The maximum current value is coming from QgH which in already in equation 2 (section 8.2.2.2 in the datasheet). The maximum current from the bootstrap is the peak current that is needed to turn on the high-side gate times the time that it takes to charge the total gate capacitance. This time is small so it can be equated by the amount of charge that is required to switch the gate. Quiescent driver current is used as well as Qrr of the bootstrap. more info on this equation can be found in section 3 of the following app note (www.ti.com/.../snva723a.pdf)
2) After the gate reaches 5V, any current required to keep it at 5V is the leakage current. The HB leakage current would be the quiescent current for the UVLO circuit ( which might be turning off the high-side in this case) as well as any current to keep the gate biased above the HS pin. To check if your leakage current is an issue you can probe a waveform of the gate to source and HB-HS bootcap voltage (with a smaller bootcap) of the high-side during turn on to see the gate/HB drop. This drop can be used to multiply by the capacitance and divided by your time delta to give how much charge the bootcap has removed during HO on time. Similar to i=Cdv/dt. does this make sense?


thanks,

Hi Jeff,

Firstly let me thank you for getting back to me so quickly with such a detailed response, it is very much appreciated.

I think your summary in the first paragraph of the reply is accurate.

Would you mind showing the workings for the bootstrap cap calculation you made? I cant seem to get close to 100's of nF, i'm probably missing something.

a) The Vdd cap value is 1uF from memory, we originally had the bootstrap capacitor as 100nF and I read that about a x10 multiplier was normal.
b,c,d) I'm no longer in the office but I will answer these queries tomorrow (UK time).

Thanks for your answer to question 1 and 2 it makes sense, unfortunately the link leads me to an error 404 not found.

Kind regards
Matt

Hi Jeff,

May I ask how you are arriving at the delta_Vboot = 0.1V calculation?

Kind regards
Matt