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UCD9090A: Configured GPIO Output doesn't add delay

John Andersen
Prodigy 50 points
Part Number: UCD9090A

See below, a configured GPIO to delay outputs Hi level when RAIL1 is "GOOD".

Results from loading/writing to Hardware(device) Flash and power cycle UCD9090A shows NO delay. Why?

  • 0
    Prodigy 50 points

    aeqj_b_v01.docxIt seems added graphics was not stored. See attached file.

  • 0 in reply to John Andersen
    TI__Guru 66120 points

    Hello John

    This issue we had talked over the phone about couple weeks ago. I though it was closed already.

    The delay on the logicl controlled GPO(LGPO) is ingored if the condtion is already met when device is out of reset. For your case, the 12V is alread regulated before UCD is out of reset. that's why 25ms delay is not observed.

    During the call, i had provided a workaround solution to use the ENABL pin of the rail to achieve the same function and also demonstrate how to achieve this on the fusion GUI. Do you have any issue to do this?

    Regards

    Yihe

  • 0 in reply to yihe
    Prodigy 50 points
    Yihe,
    Yes, the info here in your response is what you told me. I'm looking for second opinion. It doesn't make sense why GPIO logic can't run independent of voltage rail monitoring logic. Besides, I can not enable several enable pins off one rail like you suggested. Pass this issue on to other TI UCD designers for new solution.
    Thanks
    -John
  • 0 in reply to John Andersen
    TI__Guru 66120 points
    Hi John
    As explained. this is the behaviours of the device when it is out of reset. The delay is still functinal if the logic is come true after device out of reset.
    you can use multiple rails' ENABLE instead of using only one rail. just treat rail's ENABLE the same as Logic controlled GPO.

    Regards

    Yihe
  • 0 in reply to yihe
    Prodigy 50 points

    Yihe,

    If that is the case, where is the internal signal that identifies "device when it is out of reset". I don't see any such function on the GPIO Configure... STATE or STATUS list for gating functions. How does one know when the "device when it is out of reset" ?

    Is there any user documentation that details internal device operations. The funny TI videos for training lack much details for designing with devices.

    Thanks

    -John

  • 0 in reply to John Andersen
    TI__Guru 66120 points

    Hello John

    The device out of reset is determined by either the V3P3 or RESET signal. if V3V3 is above POR threshold or the external reset is above the threshold, device is considered out of reset. We will address this in the next release document.

    The training videos are to demonstrate how to use the fusion GUI to achieve individual features of the devices. we are also working on providing more contents to help customers.

    Regards

    Yihe

  • 0 in reply to yihe
    Prodigy 50 points

    Hi Yihe,

    I will try using 3.3V power input, P3V3. Can't use Reset input because its unusable until all power is up and enables are active. I notice Fusion tool can only simulate Supply Rail activity. Is there a way to simulate GPIO Output activity?

    Thanks

    -John

  • 0 in reply to John Andersen
    TI__Guru 66120 points

    Hi John

    Please make sure that P3V3 does reach power good until device is out of reset  and finishes initializtion(20ms after reset) . Currenlty GUI only support simulating the rail activities.

    Regards

    Yihe