LM5109B: 3-Phase Inverter supply shorts due to glitch on HS pin upon increasing supply

Hello Alex,

Thank you for the interest in the LM5109B half bridge driver. I am an AE with the High Power Drivers and will address your questions. Thank you for the scope plots and I will make some comments and suggestion based on these waveforms.

I have one question, the gate drive amplitude appears to be ~5V, can you confirm the VDD voltage to the LM5109B driver? The datasheet recommends a VDD range of 8V to 14V. The gate driver gate drive strength is  less with lower VDD and there is the possibility of UVLO shutdown.

The glitches or disturbance on the gate drive waveform is typically caused by the MOSFET miller charge during the Vds rising or falling time. The glitches on 0001 and 0002 are the most concerning.

There are a couple of ways to reduce the Vgs disturbance during switching. The PWB layout traces from the gate driver output to the MOSFET gate and back to the gate driver ground should be short, low inductance traces. Parasitic inductance from the layout results in a high impedance at high frequency (or dV/dt). The MOSFET Vds dV/dt can be reduced by adjusting the gate drive resistance (increase) which will reduce the peak miller charge coupled into the MOSFET gate.

Another improvement I see in motor drives, since the layout is many times not ideal, is to add capacitance on the MOSFET gate to source. This will lower the impedance on the MOSFET gate to source reducing the voltage perturbation on the Vgs.

The HI and LI inputs look very clean on plot 0007. Are these waveforms with VIN applied to the MOSFETs? Confirm that there is not voltage spikes on the driver inputs that may false trigger the driver output.

Please confirm if this addresses your question, or you can post additional questions on this thread.

Regards,

Richard Herring 

Hello Alex,

Thank you for the additional information. For the MOSFETs you mention, I see the gate charge is heavily weighted on the Qgd (gate to drain) of 98nC compared to the Qgs of 17nC. This means the miller charge can have a large impact on the Vgs due to the high ration of gate to drain Vs gate to source.

For a recommended capacitance to help, the Qgs of 17nC is with Vgs of 10V which is an equivalent capacitance of 1.7nF, if you want to balance the Qgd and Qgs you would need 9.8nF which would mean ~8nF additional, which is fairly high. Although you may want to try this as an experiment.

You might want to consider a similar FET with lower charge and lower gate charge Qgd and Cgs ratio. The IRF52N15 is a 150V, 32 mOhm FET with Qg of 60nC and Qgd of 28nC and Qgs of 18nC. This FET should be easier to drive regarding miller charge impact. The switching time can be adjusted with the gate resistance, and if additional capacitance on the gate is required, it would be a lower value of 2 to 3nF to reduce the Vgs pertubations.

For the plot you show of the ground noise. I would suggest adding a small R/C filter on the LI and HI inputs in case this noise appears on HI and LI differentially. I would suggest starting with 10 to 22 Ohms and 100pF which will have little delay impact.

Please confirm if this addresses your questions, or you can post additional questions on this thread.

Regards,

Richard Herring