LM5117: CC/CV Layout Check

Jason Galtieri

Part Number: LM5117

Hello,

I an trying to implement the CC buck in http://www.ti.com/lit/an/snva829/snva829.pdf but was having stability issues with my first layout. I posted those issues in a different thread (https://e2e.ti.com/support/power-management/f/196/p/816723/3022232#3022232) and was advised to redo the layout and get it double checked before sending it off.

Here is the updated schematic/board and thanks in advance for any feedback/criticism
CC_BuckR2.zip

over 6 years ago

0 David Baba over 6 years ago

TI__Mastermind 40040 points

Hello Jason,

Can you print layers to PDF so I can view please?

Thanks.

0 Jason Galtieri over 6 years ago in reply to David Baba

Intellectual 400 points

Here they are.

Top Copper.pdf Bot Copper.pdf

0 David Baba over 6 years ago in reply to Jason Galtieri

TI__Mastermind 40040 points

Hello Jason,

Feedback as follows.

1. Please implement AGnd pour and tie all small signal components can to the AGnd Pin.

2. Tie AGnd pin to DAP underneath pin/part.

3. Can you confirm you have routed deferentially the CS and CSG back to the device?

4. Please confirm you have routed deferentially the HS and VSW pins from Device to Gate and Source of HSFET.

5. Make Vsw polygon pour smaller by placing RC snubber and Diode to the bottom of the board. If possible rotate FETs and inductor in a way that shortens the length of the Sw node polygon pour.

6. Place a small Cap 100pF (do not install) between CSG and CS pin.

7. Place a small 100ohm resistors in series with CSG and CS

8. Please 6 and 7 by the pins of the device.

Hope this helps?

0 Jason Galtieri over 6 years ago in reply to David Baba

Intellectual 400 points

1/2 Maybe I am misunderstanding, but (in ref to picture below) I made AGND pour the blue polygon on the left, which all small signal components are grounded into. I then connect that pour to pin 6 through the via and pin 6 is then connected to the DAP. Should this be done a different way or should the two pours just be connected on the bottom layer?

3. Yes

4. Yes for SW/HS. Should Rramp be connected directly to the Source as well or anywhere on VSW pour?

5. Done

5. Done

6,7,8 Done

0 David Baba over 6 years ago in reply to Jason Galtieri

TI__Mastermind 40040 points

Hello Jason,

Please refer to the document I sent and make a small Agnd poly pour as I showed, and then have this pour directly route back to the AGnd pin on the same side of the board.

As for the Ramp resistor, no need to route to source of FET. Its fine as shown.

Hope this helps?

0 Jason Galtieri over 6 years ago in reply to David Baba

Intellectual 400 points

Like this then?

0 David Baba over 6 years ago in reply to Jason Galtieri

TI__Mastermind 40040 points

Hello Jason,

Yes, that is correct. please make sure you have vias on the device DAP that goes to the Gnd layer.

Thanks.

Power management

Power management forum

LM5117: CC/CV Layout Check