Other Parts Discussed in Thread: TINA-TI,
Tool/software: TINA-TI or Spice Models
Hi,
Great news that the earlier TPS2492 TINA model issues have been fixed. I thank you for this. However in recent simulations I noticed that now with the model released 27/3/19; the zener between OUT and GATE seems to be missing, or not working as expected. If a fault condition occurs which triggers the 125mA gate pull-down whilst the OUT pin in sitting well above the max VGS of the pass FET. The gate is rapidly pulled to 0V! for approx 100uS and then jumps back to within a few 100mV of the OUT voltage when the strong pulldown is released. If I measure current into the OUT pin, I would expect to see this 125mA being pulled into the OUT pin through the internal zener and down to GND. It does not occur. Instead the gate drops fully to 0V and the VGS of the pass FET exceeds its tolerances. I also notice that after the 100uS strong pull down, in order to return the gate back to a voltage equivalent to the forward drop of the zener, the internal current source in the model reverses and for a very short period it pushes 100mA into the gate until it returns to the correct voltage relative to the OUT pin.
Furthermore the strong pull down current seems to only exist for the short period while GATE sits above the voltage of the OUT pin, once the GATE falls below OUT the pull down current drops to 25mA for the remainder of the 100uS. Still further, even though I still assert OV well beyond this 100uS period, the holding pull down of 2mA does not persist after the 100uS initial strong pull down.
If I place an external zener between OUT and GATE, sure enough the VGS is held within tolerances and things behave more like what is expected. (still missing the weak pull down)
This may all sound a little pedantic of me, however, in the process of modelling the external FET and downstream effects these are rather important features. These behaviours of the internal current source of the TPS2492 model are causing unrealistic behaviour, the rapid switches in current direction leads to convergence problems in SPICE and obviously one of the first things I do when simulating is to watch the VGS of the power FETs. This one would have been dead a long time ago if the IC acted this way.
I know your team is busy and I appreciate the fact that these tools are all made freely available to help us, but simulations before hardware are an attempt to identify these transient behaviours and to alleviate anything unexpected before proceeding to hardware. I'm sure you understand.
Perhaps you could take a closer look.
All the best
Aidan
