TPS7A4701-EP: Not achieving 4 uVrms output noise on TPS7A4700 LDO - possibly due to my layout?

Hello Thomas,

Your question came through Friday evening, so it is likely that no on will be available to answer until Monday morning.

Hello Daniel,

Thanks very much for your response. The documents you provided are very nice for future reference, and give some good suggestions. I was already aware of much of what is described, and have attached some updated measurements of the +12V output rail to try to address some concerns. In the attached pdf, you can see that I have tried both the "clip on" ground, and the "pigtail" ground probe techniques. I did not do the direct coaxial cable method, because I don't have one that I'm willing to hack up at the moment. You can see from the attached scope shots that the pigtail ground improves the signal significantly, and therefore is likely due to pick up. The measured rms is with the pigtail method is still seen to be 740 uV rms. You can also see that the noise on the input is not too bad (3 mV rms).

I did not add any high frequency decoupling capacitors, because I tried to follow the guidelines on the datasheet for the chip, as well as the evaluation board for this chip.

You picked up on the little copper areas which might act as antennas - this was just an oversight on my part during the design of this iteration, and will be fixed on the next version.

The +12V and -12V are disconnected, because I wanted to be able to test the power supply section without worrying about powering the rest of the board, which may interfere with the tests I am performing.

Can you recommend anything else which may be causing this? Or perhaps even a better way to do things? Is there a combination of ferrite beads / inductors / capacitors that I can add to the output of the TPS in future versions that would kill this ripple? Is there something I have done badly with the ground plane, or a better way to do it?

TI_Question 2.pdf

Hey Thomas,

Are there any switchers near the output of this device?

Its strange to ave such periodic noise on an LDO.

It looks as if a switching converter is coupling the noise to the board.

Thanks,

Daniel

Hi, yes the device U1 is an isolating DCDC converter: 

IR1215S

I have a requirement for isolated power supply on this design.

Hey Thomas,

I might suggest disabling the switcher and seeing if the noise goes away.

If that is not possible, you can see if the noise is in sync with the switching clock of the DC/DC.

Thanks,

Daniel

I am not able to detach the switcher in this instance. The noise is indeed at the switcher's frequency, but the reason I used the TPS is because the datasheet says that it is ideally suited for post DCDC converter regulation. Therefore, I would expect that it can suppress the switcher noise a little more effectively than the results I am getting?

Hey Thomas,

While the LDO can be good for filtering DC/DC converter noise, the noise would have to be at the input of the converter.

When the noise is at the input of the converter it can be reduced by the PSRR of the LDO.

The LDO however is unable to do anything about noise that is coupled from the output of a DCDC to the output of the LDO as it never goes through the LDO and can't be reduced by the PSRR.

Thanks,

Daniel

I understand. So, I am trying to understand why the noise is making its way to the output of the LDO in this particular case. Is it something to do with my ground plane arrangement. Or perhaps something else in the layout?

Hey Thomas,

Ground plane arrangement would be my first guess.

For DC/DC switchers you always have to be careful about the high current path and making sure that the current doesn't have large loops to radiate noise or go across any sensitive nodes.

Either of these things can cause noisy grounds that will interfere with the output of your LDO.

Thanks,

Daniel

Okay, can you point out specific problems and areas with the layout around the DCDC and LDO on my layout pictures, which would lead to these things you describe? Can you point out where such loops and high current paths are in my design?

Thanks Daniel. So could you point to  anything specific in my design where I did something with the ground plane that could cause the issue? Or point to where the high current paths would be, with a suggestion of how to do it instead? I would like to know how to fix the issue around the DCDC and the LDO, to determine whether these chips are suitable for my application.

Hey Thomas,

Below is a good starting point on the DC/DC converter:

http://www.ti.com/lit/an/slyt614/slyt614.pdf

A lot of what I told you for the LDO will be true for the DC/DC converter.

Your large current loops will be dependent on which converter it is.

Simply follow the path your input current will take or output current will take.

An example:

Thanks,

Daniel

Hi Daniel,

Thanks once again for a nice reference. I have read it thoroughly. However, I am struggling to see how I can apply the tips given in that document to my specific case. The document describes placement of output snubber, inductor, small signal connections (for feedback, etc), digital stuff (such an an enable pin), etc. However, none of these are really relevant to the brick-style converter that I am using (attached is the datasheet for the IR1215S). The chip doesn't have any of the things mentioned in the document, and only has 5 pins (all of which are power inputs and outputs positive and negatives). The one thing I do have is output capacitors, but I believe I have already placed them as close as possible to the output of the converter, as recommended by the document you provided. Do you have any literature which is more suited to this type of component?

Would you be able to just sketch over the top of my layout diagram in the first pdf, to show where the high current paths you are talking about would be flowing, and suggest an alternative way to rearrange things so that this noise doesn't reach the LDO output?

Thanks again,

SF_IR.pdf

Hey Thomas,

I am not allowed to comment on competitor devices or the application of them.

Thanks,

Daniel

Ofcourse, I understand. Can you suggest a solution using only TI branded components? I am happy to purchase a new DCDC converter from TI if it will do the job. My goal is to take an input of +12V and produce low noise +12V and -12V power supply rails for some low noise analog circuitry consisting mainly of op amps. I am open to suggestions using TI parts only.

Thanks!

Hey Thomas,

What is the current requirement on each rail?

Also, what is the radiation requirement/temperature requirement?

Thanks,

Daniel

The current requirement of each rail is approximately 100 mA. I have no requirements at the moment on radiation or temperature.

Hey Thomas,

Can I ask why you are using the TPS7A4701-EP then?

The -EP signifies an increased temperature range among other things including an increase in price.

Are you looking for commercial grade products?

Thanks,

Daniel

I am not using the TPS7A4701-EP, but when I created the question on the forum, that was the closest part to that which I am actually using that I could select from the options. In fact I am using the TPS7A4700.

Hey Thomas,

This is because the TPS7A4700 is a subset of the TPS7A47.

Luckily the devices are more or less equivalent, thus most of what I said is still valid.

For part selection though, I suggest you try using Webench.

If you have any further questions on the LDO please repost them to a new E2E post under TPS7A47.

Thanks,

Daniel