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LM5050-1: Can you help me to figure out what's wrong with my TINA-TI Spice circuit model of LM5050-1?

wil wang
Prodigy 60 points
Part Number: LM5050-1
Other Parts Discussed in Thread: TINA-TI,

In my application, I have 2 power input module in the chassis, I decided to use LM5050 to prevent current reversal when another module attached to a backplane, on which there's already has a module on, the picture below is my test circuit in TINA-TI, I place a voltage controlled switch in between the 2 output of power module.  

I am totally confused with the result:

1.  Why the 12V_IN1/12V_IN2 ramp up sumultanously?

On a real board, the LM5050 do prevent the reversal conduction, and I have capture the in-rush current waveform on a real board, surprisingly, the current is very big compare capacitance on the output of the LM5050(C1/C4 in the test circuit) , from the waveform, the charges is estimated to be 112uC(44.8A * 5uS * 0.2), and capacitance of C1 or C4 is 9.3uF(charged to12V, and the Qg(total) of NMOS is 30nF), almost twice the actual capacitance, so

2. What's the other factors I need to count in when analysis the inrush current?

Thank you. 

(PS: the encloures are the spice model for NMOS and TINA-TI circuit file FYI)

LM5050-X2.TSCPSMN1R5-30YL.lib

  • 0
    TI__Genius 16305 points

    Hello Wil Wang,

    I am looking into this issue, let me check and get back within next two days.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    TI__Genius 16305 points

    Hello Wil Wang,

    On the real application board, inrush current is determined by the amount of capacitance at the input of LM5050-1 and output of LM5050-1.

    For LM5050-1 application here, Inrush current can be calculated by  I_inrush = (C_IN + C_OUT) * dVin / dt. Here dVin / dt is rate of change in input power supply voltage.

    C1 and C4 does not contribute to inrush due to the presence of R1 and R3 100ohm resistors which will limit the current.

    Inrush is mainly contributed by C2 and C5 and any other additional capacitance at the IN pin.

    I am checking the simulation waveforms and get back to you today.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    TI__Genius 16305 points

    Hello Wil Wang,

    In the TINA TI model file, can you try grounding voltage controlled switch SW1, VG1 to GND with low resistance path.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    Prodigy 60 points

    Hi, Kari,

    Do you mean lower the resistance of R4? 

    Yes, I changed it to 5 ohms, but result is no different.

    And thank you for your clearification regarding the inrush current, but I wonder how could the capacitor connected to VIN pin(C3 in the schematic) contribute to the magnitute of the inrush current, since it is blocked by the NMOS at the moment of LM5050 powering up.

    Again, I measured the inrush current when capacitor(C2/C5) at output of LM5050 are removed, still, I get lots of inrush current, I do know where they go.

  • 0 in reply to wil wang
    TI__Genius 16305 points

    Hello Will Wang,

    I was able to check the TINA-TI simulation file. Issue is due to same net label assigned to input of 1st LM5050 "IN" and the same name assigned to input of 2nd LM5050 "IN". Since both have same net name, Input node of second follows input of first LM5050.

    I corrected the names and simulation runs fine.

    Regarding the inrush, can you share the full schematic (main what is at the front of LM5050 and after LM5050, amount of capacitance is needed to calculate the inrush. 

    Inrush calculation is simple as i discussed earlier, we just need to know the total amount of capacitance seen at the input.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    TI__Genius 16305 points

    Hello Wil Wang,

    Let us know if you have gotten a chance to look at the question.

    Regards,

    Kari.

  • 0 in reply to Karikalan Selvaraj
    Prodigy 60 points

    Hi Kari,

    after deleting the duplicated net ID, I got meaningful result now, I use this device to set up 1+1 redundant power supplier schem, and it required to be hot-swappable, the VRM(PS1/PS2) on the board can source 12V/75A, and support droop-load-sharing, beside the Oring protection in case of VRM failure, I need to make sure that the massive decouple capacitance on ouput ot the VRM would not pull-down the 12V of backplane when an unpowered power board plugged, ie. the NMOS should block current reversal.

    But the measurement indicate that the MOS would conduct some current when board plug occurs（see pitcuture below, channel 1/4 are Vgs/Id of NMOS respectively).

    The simulation reveal that it might result from the parasitic inductance of the PCB, and in some cases, the MOS can be fully opened, resulting very large inrush current(See my test circuit and result waveform)

    My question is:

    Is there anything I can do, beside layout precautions in datasheet , to further minimize the reversal current on board plug?

  • 0 in reply to wil wang
    TI__Genius 16305 points

    Hi

    MOSFET is turned off when Vgs  is 0V. However when MOSFET turns off , reverse current is cut off and due to the parasitic inductance we see ringing on the voltage and current waveform.

    No reverse current is seen after this and this should not cause backplane supply to droop.

    Regards,

    Kari.