ULQ2003A: Rising time and falling time

Hi Dmello,

I am sorry for the lack of explanation,
but your answer is the delay time from when the input signal is input until it is output as an output signal,
but the purpose of this question is rise (fall) of the output signal itself Time (in Figure 17, the slope of output).
*This is considered to be related to the transistor characteristics of the internal circuit.
Sorry for your inconvenience but I would appreciate your reply after confirming the attachment.

rising falling time.pdf

Best Regards,
Tom Liu

Hi Liu,

What is your concern exactly? Is it based of the frequency that can be used to run the part?

Unfortunately, the output rise and fall time is not specified by TI. We can guarantee the t_PLH and t_PHL. 

This spec is typically at 1us and maximizes at 10us and also accounts for 50% of the rise time of the output and the deadtime between input and output. Assuming this deadtime is zero, I would say that the maximum output rise time would be in the range of 10us-20us but this is an extremely conservative estimate.

Hi Lui,

I saw that you posted a duplicate thread with more detail. Hence I am going to close this one.

https://e2e.ti.com/support/power-management/f/196/t/834452