UCC28070: About GDApin, GDBpin and external clock timing and Max Duty.

Hello

thank you for your answer.

See equations (9) and (10) in data sheet session 7.3.4.

From this equation, we believe that the maximum duty can be increased by increasing the sync pulse width (Dsync) and decreasing the maximum duty setting resistor (Rdmax).

Therefore, if the sync pulse (fsync) is set to 200 kHz, the sync pulse duty is set to 35%, and Rdmax is set to 47 kΩ, the maximum duty is calculated to be about 98%.
However, when measured with a real machine, the maximum duty was 83%.

Question
1 The maximum duty can be increased by increasing the sync pulse width (Dsync) and decreasing the maximum duty setting resistance (Rdmax).
Is this idea correct?
2 In the calculation, the maximum duty was 98%, but the actual machine showed a difference of 83%.
Why is it so different? (What can be considered?)

thank you.

Hi Masa-san,

The sync pulse width must be minimised, min recommended value 200ns, this ensures the sync pulse does not significantly reduce the max on-time for the PFC fet.

The rising edge of the sync pulse syncs the master clock and the falling edge of the sync pulse starts the max duty cycle timer. That is why the RDmax resistor value must be adjusted when using an external sync pulse and it must also take account of the sync pulse width.

Where did you get the max duty cycle value of 98% from ? Please note that there is a risk that the CS transformers can saturate if they are not correctly reset.

Typical Dmax for the UCC28070 is given as 95% in the datasheet.

There is an additional delay associated with processing the negative edge of the sync pulse of 50ns to 100ns which may reduce the max duty cycle further.

Regards

Peter

Hello.

thank you for your answer.

Now, I want to confirm.
The other day's answer
The sync pulse width must be minimised, min recommended value 200ns,

There is.

Does this mean that the sync pulse width should be set to less than 200ns?

Or do you need to set the pulse width wider than 200ns because of misunderstanding?
If so, what is the maximum pulse width?

Thank you.

Hi Masa-san,

Sorry for the late response to your last question, I was OOO for on-site support recently. The pulse width should be between 100ns and 200ns, the wider the sync pulse width the more it reduces the maximum available duty cycle.

Regards

Peter