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LM5066: Power FET fails when testing LM5066 for "Startup into short"

flavio
Intellectual 410 points
Part Number: LM5066
Other Parts Discussed in Thread: CSD19536KTT

I am testing hotswap circuit (lm5066) for "startup into short". The output of the LM5066 is shorted then I enable the device. in a good case, LM5066 has to realize the huge current in a usec and Cicuit Breaker (CB) gets activated and hold the gate low and as a result shut down the output. however I am seeing that the power FET (CDS19536KTT) is burning when I run this test. below are the status of afew registers after the failhecking registers after fail:

D7h=00h

80h=10h

E1h=08BAh

Register D7 is 00h so no safety feature is disabled.  register 80h, i see that the bit 7 (CB fault) is not even triggered.

Why the CB is not getting triggered?

  • 0
    Intellectual 410 points

    adding the scope capture.

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    Can you please share the schematic and filled up design calculator to check the design margin. The design calculator is available at http://www.ti.com/product/LM5066/toolssoftware

    The following videos help you on how to use the design calculator.

    https://training.ti.com/node/1133677  

    https://training.ti.com/node/1133673  

    https://training.ti.com/node/1133664  

    https://training.ti.com/node/1133681  

    BR, Rakesh

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    In schematic, I see 1uF (=1000 nF) for the timer cap which is too long for the FET to survive for this design. 

    Use 10nF for the timer cap and check.

    BR, Rakesh

  • 0 in reply to Rakesh
    Intellectual 410 points

    Hi Rakesh,

    Good observation. Older boards had 10nF, not sure why the cap is changed to 1000nF. will 10nF try and report back.

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Ok.. Flavio.

  • 0 in reply to Rakesh
    Intellectual 410 points

    Hi Rakesh,

    I replaced the Timer cap to 0.01uf. however the "Startup-into-short" failed burning the power FET again. we need to know why the safty features aren't kicking in. Why the CB is not working? with the timer set to 0.52mS, LM5066 has to know the short way before the supply knows.

    =============

    before start:

    register d7=00

    register e1=0860

    after failure:

    register d7=00

    register e1=0888

    ================

    scope captures attached for your review, basically the source supply realizes the short after almost 20mS and tried the shut down. by that time the FET is already gone.

    ch1=54vin (drain)

    ch2=gate

    ch3=out to the board (source)

    ch4=enable

    +++++++++++++

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    Correct. It should cut-off in 0.52ms. Can you check input current and timer voltage ?

    Please share me the layout to have a look.

    BR, Rakesh

  • 0 in reply to Rakesh
    Intellectual 410 points

    Hi Rakesh,

    I  ran "HOT SHORT" test, and it passed. Register E1 after passing was 0863. So CB fault  is set. see the capture below. (CH1=Vin (drain), CH2=Gate, CH3=Vout (Source), CH4=Enable).

    Then I ran "Start up into Short test" on the same board and it failed. Power FET got shorted, the 54V power source had to shut down (yellow line ch1). register E1 after fail is 0888. CB is not set.  register D7 is 00 both before and after the test in both test cases, so none of the safety features are masked, but what could be the difference?

    I'll add layout later today.

    AA

  • 0 in reply to flavio
    Intellectual 410 points

    Hi Rakesh,

    attached is the layout. A question on the turning on the LM5066. does the FET has to be off (register 01=00h) before hotswap Enable or vice versa, FET enabled (register 01=80h) then hotswap enabled?

    AA

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    Can you double check the value of Rpwr (R24)?

    As I mentioned, Can you check input current (at 54V input connector) and timer voltage ? 

    A question on the turning on the LM5066. does the FET has to be off (register 01=00h) before hotswap Enable or vice versa, FET enabled (register 01=80h) then hotswap enabled?

    There is no criteria on this sequence, you can do either way. 

    BR, Rakesh

  • 0 in reply to Rakesh
    Intellectual 410 points

    Hi Rakesh,

    As you know our design have 3X Power FET’s ,SOFTWARE controlled enable pin and software controlled Gate ON/OFF.

     The way we our software do is like below as soon we have 54V input on in sequence.

     

    1. LM5066 Write 0x00 to OPERATION (0x01) reg to switch MOSFET Off(I2C access)

    2.Turn on V54V_SWAP rail via HS_ON_ISO...(EN pin)

    3. LM5066 Write 0x80 to OPERATION (0x01) reg to switch MOSFET On(I2C access)

     

    With above condition—when we do a fixed  short at hotswap output ,  then plug 54V input and use our software to turn on the hotswap as above—we have FET blow up.timer cap change has no impact

    With above condition—when we do a live short after software turns on the hotswap by above steps,we have FET blow up. Timer cap change has no impact.

    Then we want to isolate the software control,hard tied the enable pin of hotswap with divider to 54V to set OV/UV/enable,removed the two power FET’s and made it similar like HFCB board (single FET and no software control and it works with short test)  for our surprise the hot swap protects the FET with live short as well as dead short on power up.

    We have tried this many times all success.

    Now we like to know whats the dependency with 2X extra FET,Enable pin impact etc for protection.Any thing on our circuit need to be changed to support 3X FET’s?

    Please review the comments and lets us know.

     

     

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    I have some issue connecting to VPN to reply over email and hence replying here.

    It is surprising to see the dependency of SOFTWARE control sequence on the FET fail cause. I never faced this case before. Can we get on a call (on Monday) to discuss more.. I will duplicate the issue on my bench and then take it forward.

    Best Regards, Rakesh

  • 0 in reply to Rakesh
    Intellectual 410 points

    Hi Rakesh,

    We noticed two dependencies,

    1- Software control of the Enable pin.

    2- number of POWER FETs being in parallel. It seems with more than 1 FET, the gate oscillates. see the capture below.

    Monday meeting is good. Either I or Daniel will set it up.

  • 0 in reply to flavio
    Intellectual 410 points

    Missed the scope capture:

  • 0 in reply to flavio
    Intellectual 410 points

    SOA calc.

    1.  t_startup for (LD) = dt=c8*dv/I=0.1uF*60/20uA= 0.3S=300mS
    2. I(inrush LD)= 1080uF * 60V/300ms=0.162A
    3. PD_startup (LD)=Vin * I(inrush)=60V * 0.216=9.72W
    4. For CSD19536KTT MOSFET: SOA current at 60V, 300ms = 2A (assuming 300mS is following the DC red line closely on SOA figure, checked with TI)
    5. FET can support 60V*2A=120W for 300ms at Tambient of 25C
    6. derate for Tambient of 85C:   Pderated = 120W * (Tjmax – Tambient) / (Tjmax – 25) = 120 * (175-85)/(175-25) = 72W
    7. SOA margin during startup = Pderated / PD_startup = 72W /9.72=7.4

     

  • 0 in reply to flavio
    Intellectual 410 points

    Hi Rakesh,

     

    We shorted R135E and repeated the hot short test.

    With 1 FET, test pass

    With 2 FETs it failed.

     I also added 2 Schottky diodes to the output of the hotswap (Source) but that did not help.

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    I will configure EVM (http://www.ti.com/lit/ug/snvu444/snvu444.pdf) as per your schematic and test with 3 Hot-swap FETs but at hand I don't have CSD19536KTT FETs. I can test with PSMN4R8-100BSEJ FETs.

    I would be able to test by this Friday.

    Best Regards, Rakesh

  • 0 in reply to Rakesh
    Intellectual 410 points

    Hi Rakesh,

    Some more updates on my side, I think we might be getting close to a conclusion.

    • As you know we use LM5066 in multiple designs. each design has different number of power FETs connected to LM5066 gate drive pin. below are the list:
        1. LD=1 LM5066+3 power FETs
        2. SOD=1 LM5066 +2 power FETs
        3. HFCB= 1 LM5066 + 1 power FET
    • As you already know LD fails both "STARTUP INTO SHORT" (SIS), and "HOT SHORT" (HS). I lost LD board, so I started working on SOD.
    • SOD board has 2 FETs, but I started with only 1 FET. both SIS and HS tests passed. below are the captures.

     I added a 2nd FET to SOD and repeated the test. SIS Failed. we see Oscillation at the gate. causing source to osculate.

    • HFCB board has 1 FET and it solidly passes the SIS and HS tests.

    Why we see oscillation with more than 1 FET at the gate pin?

  • 0 in reply to flavio
    TI__Guru** 105611 points

    Hi Flavio,

    I will get back on this query by today

    Best Regards, Rakesh

  • 0 in reply to Rakesh
    TI__Guru** 105611 points

    Hi Flavio,

    I have communicated over email and hence closing here to avoid duplicate efforts.

    Best Regards, Rakesh