UCC28950: Device mode settings & toggling guide

Hello Leo

I would not recommend that you switch from Master to Slave modes by switching the RT resistor. The device was not designed for that condition and may not function correctly.

However, you can switch from Slave to Master modes by setting the device up as a slave and using an external SYNC source to deliver at least 2 negative going edges to the SYNC pin. You can then either continue with the SYNC pulses or stop them. If you stop them then the controller reverts to its own internal oscillator. You can restart the SYNC pulses to achieve synchronisation again.

I'm not sure what you are trying to achieve with the compensation networks but I'd suggest that you configure the on-board error amplifier as a follower (EA- to COMP) and make any compensation configuration changes you want in the external error amplifiers. If you are trying to implement a CI/CV characteristic you should look at the reference design PMP8740 http://www.ti.com/tool/PMP8740

Regards

Colin

Hi Collin,

Thanks for the quick response! Reason I'm asking is because one of our customer was asking can they achieve master/slave mode toggling by connecting the external resistor RT between the RT pin to VREF and place an 825-kΩ resistor from the SS pin to GND in parallel with the SS_EN capacitor.

Based on my understanding, in their application they intended to perform the switching frequency in Master mode while the feedback (EA, COMP) to be in Slave mode. But is it necessary to perform mode switch to get things done?

Regards,

Leo 

Thanks Leo for trying to get answer for me.

Hi Colin,

We are not going to toggle between master/slave modes during operation.

1. Can we do a mix of mode by connecting the external resistor RT between the RT pin to VREF and place an 825-kΩ resistor from the SS pin to GND in parallel with the SS_EN capacitor? We believe that we can have master mode for switching frequency while slave mode for feedback (EA, COMP). We are going to implement feedback and loop compensation before entering EA+ pin. I cannot find such mixed mode info in UCC28950 related documents.

There are several more questions as below.

2. Why equation-56 and equation-88 in UCC28950 datasheet are different? VdsQA and Vds_spec are the values found from its MOSFET spec. Vinmax and VdsQE are the actual operating values.

Equation-56:

Equation-88:

SPP20N60CFD Typ capacitance:

Based on the above typical capacitance curves, Coss is inversely proportional to Vds. So, Equation-56 should be correct while Equation-88 should be corrected where Vds_spec should be divided by VdsQE, right?

3. Is Equation-85 correct? Because a1 is the ratio of 1-3 to 10-12 or 7-9. It should be: Vinmax/(a1/2), right?

Equation-85:

Vitec 75P8107 turn ratio:

Vitec 75P8107 Schematic:

Phase-shift full bridge schematic:

4. Are QE and QF switching at Vds of Vinmax/(a1/2)? They do not have ZVS? Their switching loss is the dominant of their total loss.

Regards,

KK

Hi Colin,

1. What PMP8740 did is different where its SS/EN pin is not connected to 825kOhm to be in slave mode. Although its CI and CV regulation feedback are done externally, it is in master mode for both pins. What is the reason to have mode selection at SS/EN pin? Isn't it sufficient to have a mode selection only on RT pin?

2. Since 25V is from its datasheet, why 25V is for numerator at Equation-56, but is for denominator at Equation-88? Shouldn't 25V be consistent for numerator at both equations?

3. Thank you for your clarification.

4. Since SRs always switch at zero volt, why equation-94, which is the power loss of SR, includes switching loss, which is circled in blue.

Equation-94:

Below are several more questions:

5. Is equation-166 for RT correct? It does not match the RT equation converted from equation-10 for Fsw.

6. Which equation for RTMIN is correct? Equation-164 from datasheet or equation-140 from App Report?

Equation-164 from datasheet:

Equation-140 from App Report:

7. Is Equation-102 correct? a1 is efficiency?

Equation-102:

Regards,

Kok Khuan

Hello KK

1. What PMP8740 did is different where its SS/EN pin is.......  The Master / Slave mode is set by the resistor at the RT pin. If the resistor is connected to VREF the controller operates in Master mode with synchronisation pulses output at its SYNC pin. If the resistor is connected to GND the controller operates in Slave mode and will synchronise to an externally supplied synchronisation signal. The 825k resistor at the SS/EN pin has no influence on the mode selection but we recommend it for use in Slave mode to prevent a possibility that the SS/EN pin charges past its maximum. The 825k resistor is not needed in Master mode but there are no disadvantages if it is present.

2. Since 25V is from its datasheet, ...... 25V is just the point at which the Coss was specified for the particular devices chosen for the primary and SR FETs. It's just a coincidence that the same voltage was used for the two devises. The reason one is in the numerator and one in the denominator is that in one application the working voltage is greater than the test voltage so Coss_avg would be lower and in the other application the working voltage was lower (19.5) than the test voltage so Coss_avg would be greater. The 19.5V was in fact an error, it should have been 39V and in that case the Coss_avg would be lower than the value in the datasheet. If the data sheet gives an equivalent Coss value then that would be a better value to use.

4. I think EQ 94 is wrong. The SRs are switched at zero volts so there are no Coss related losses. The SR losses are conduction losses (I^2 R), body diode conduction losses during the transition (Vf * If(t)) and gate charge losses (0.5*Cg*Fsw*2, the factor of 2 is here because you lose energy in charging the gate and again in discharging it). I'm sorry but I don't have any more details on these.

5/ Eq 166 is incorrect, the final x2.5x10^3 should not be there and the result is in kOhms. Eq 10 is correct and corresponds to the graph in Fig 35.

6/ The equation in the data sheet is more correct. The app note was written during the device development phase and we changed the equation to the one in the data sheet because it gives a better fit to the curves in Fig 34.

7/ Eq 102 is correct. The RMS transformer primary current is the sum of the RMS input current and the RMS capacitor current. Rearranging these we get ICin^2 = Ipri^2 - Iinput^2. The values under the square root sign must both be currents squared and Pout/(V*a1) is the output current reflected into the primary through the transformer turns ratio. The equation neglects the efficiency so you could modify it to use Pout/(V*a1*n). the equation uses VINMIN because this is the worst case input voltage.

Regards

Colin

Hi Colin,

1. Thank you for making us clear.

2. I agree with you that Coss_avg would be lower than Coss_spec for working voltage greater than test voltage. Let us look into equation-88 in details as captured below.

Capture above is from its datasheet where its working voltage is 19.5V, which should be 39V. Just assume the working voltage is 19.5V first. 19.5V working voltage is lower than the specified test voltage at 25V. Calculated Coss_avg based on equation-88 is 1.6nF, which is lower than 1.81nF of Coss_spec. This result shows that Coss_avg would be lower than Coss_spec for working voltage lower than test voltage. This is contradicting to what we agree.

4. Thank you for your clarification. The gate charge loss equation should include Vg.

5. Thank you for your clarification. Fsw should not be divided by 2 in equation-166.

6. Thank you for your clarification.

7. Output current reflected to primary = Pout/(V*a1*n) with V=Output voltage. However, in equation-102, V is input voltage, VINMIN. So, Output current reflected to primary should be without a1 term, which is Pout/(V*n), right?

I have another question as below.

8. For Rsum calculation, should I use equation-144 to equation-148 from App Report or equation-168 to equation-172 from datasheet?

Regards,

KK

Hello KK

2/  You are correct - I should have spotted that.

7/ You are correct - the a1 term should be the efficiency not the turns ratio - Here's my calculation

8/ You should follow the method in the data sheet because that includes the stabilising effect of the magnetizing current in the calculation. I would make two points - First: the numerical result for eq 167 is wrong Second: You should use Vin MIN in the calculation for M_mag (eq 169) because that is where the slope of the magnetizing current is least.

You may find that you don't actually need much additional slope compensation.

Regards
Colin

Hi Colin,

Thank you for your clarification.

For phase shift full bridge, the MOSFETs switch on at zero voltage. Do they switch off at zero current? If no, why there is no MOSFETs switch-off loss included?

Is there any recommended technical info on designing phase shift full bridge magnetic parts such as transformer?

Regards,

Kok Khuan

Hello KK

the MOSFETs switch on at zero voltage but they do not switch off at zero current. I expect that we did not include switch off losses because the MOSFET channel can be turned off in a much shorter time than the ZVS transition times. If the MOSFET is turned off slowly, then it will dissipate some of the energy that would otherwise be available to drive the ZVS transition so fast MOSFET turn-off is advisable.

There is some introductory material on transformer design in the TI library at http://www.ti.com/ww/en/power-training/login.shtml  - use the keyword 'magnetic'. The Magnetics Design Handbook is a good introductory text and the article Transformer and Inductor Design for Optimum Circuit Performance is also good.

If you need an in-depth and detailed text, then I'd suggest you take a look at 'Transformers and Inductors for Power Electronics: Theory, Design and Applications' by W.G. Hurley, W.H. Wölfle.

https://www.wiley.com/en-us/Transformers+and+Inductors+for+Power+Electronics%3A+Theory%2C+Design+and+Applications-p-9781119950578

Regards
Colin